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| author | Paul Fertser <fercerpav@gmail.com> | 2011-10-10 11:19:23 +0400 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-10-25 11:17:43 +0200 |
| commit | 6571534b600b8ca1936ff5630b9e0947f21faf16 (patch) | |
| tree | bd702bc1929f14abd19d2f9f932ce827304f6445 /arch/arm/plat-mxc/include/mach/iomux-v3.h | |
| parent | d093d5bbdb255b64d9dd6478d1d534e2101f9a70 (diff) | |
| download | linux-6571534b600b8ca1936ff5630b9e0947f21faf16.tar.gz linux-6571534b600b8ca1936ff5630b9e0947f21faf16.tar.bz2 linux-6571534b600b8ca1936ff5630b9e0947f21faf16.zip | |
plat-mxc: iomux-v3.h: implicitly enable pull-up/down when that's desired
To configure pads during the initialisation a set of special constants
is used, e.g.
#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
The problem is that no pull-up/down is getting activated unless both
PAD_CTL_PUE (pull-up enable) and PAD_CTL_PKE (pull/keeper module
enable) set. This is clearly stated in the i.MX25 datasheet and is
confirmed by the measurements on hardware. This leads to some rather
hard to understand bugs such as misdetecting an absent ethernet PHY (a
real bug i had), unstable data transfer etc. This might affect mx25,
mx35, mx50, mx51 and mx53 SoCs.
It's reasonable to expect that if the pullup value is specified, the
intention was to have it actually active, so we implicitly add the
needed bits.
Cc: stable@kernel.org
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/iomux-v3.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/iomux-v3.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index ebbce33097a7..45099566fecc 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -89,11 +89,11 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_HYS (1 << 8) #define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6) -#define PAD_CTL_PUS_100K_DOWN (0 << 4) -#define PAD_CTL_PUS_47K_UP (1 << 4) -#define PAD_CTL_PUS_100K_UP (2 << 4) -#define PAD_CTL_PUS_22K_UP (3 << 4) +#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) +#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) #define PAD_CTL_ODE (1 << 3) |