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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-11-24 08:24:29 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-11-24 08:24:29 +0100 |
| commit | 2a85927c79634e89b9cd683dd2bae65966d9b216 (patch) | |
| tree | 5e922b0f26e4099b6bcad65d2d5ea42e166ff068 /arch/arm/plat-mxc | |
| parent | 3561d43fd289f590fdae672e5eb831b8d5cf0bf6 (diff) | |
| parent | 124bf94a9f9b52341562628cd56b252e7d820ee8 (diff) | |
| download | linux-2a85927c79634e89b9cd683dd2bae65966d9b216.tar.gz linux-2a85927c79634e89b9cd683dd2bae65966d9b216.tar.bz2 linux-2a85927c79634e89b9cd683dd2bae65966d9b216.zip | |
Merge branch 'imx-for-2.6.38' of git://git.pengutronix.de/git/ukl/linux-2.6 into imx-for-2.6.38
Diffstat (limited to 'arch/arm/plat-mxc')
45 files changed, 1486 insertions, 936 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 64e3a64520e0..a31fa161bb6d 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -21,10 +21,6 @@ config ARCH_MX2 config ARCH_MX25 bool "MX25-based" - select CPU_ARM926T - select ARCH_MXC_IOMUX_V3 - select HAVE_FB_IMX - select ARCH_MXC_AUDMUX_V2 help This enables support for systems based on the Freescale i.MX25 family @@ -51,7 +47,6 @@ endchoice source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-mx3/Kconfig" -source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mxc91231/Kconfig" source "arch/arm/mach-mx5/Kconfig" diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 0be1ac7f421b..175e3647bb27 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void) audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); } #endif -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) { audmux_clk = clk_get(NULL, "audmux"); if (IS_ERR(audmux_clk)) { @@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void) } audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); } -#endif +#endif /* if defined(CONFIG_SOC_IMX25) */ audmux_debugfs_init(); return 0; diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 735776d84956..e9bcefe79a43 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c @@ -17,6 +17,7 @@ */ #include <linux/kernel.h> +#include <linux/slab.h> #include <linux/init.h> #include <linux/err.h> #include <linux/platform_device.h> @@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) return ret; } -struct platform_device *__init imx_add_platform_device(const char *name, int id, +struct platform_device *__init imx_add_platform_device_dmamask( + const char *name, int id, const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data) + const void *data, size_t size_data, u64 dmamask) { int ret = -ENOMEM; struct platform_device *pdev; @@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id, if (!pdev) goto err; + if (dmamask) { + /* + * This memory isn't freed when the device is put, + * I don't have a nice idea for that though. Conceptually + * dma_mask in struct device should not be a pointer. + * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 + */ + pdev->dev.dma_mask = + kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); + if (!pdev->dev.dma_mask) + /* ret is still -ENOMEM; */ + goto err; + + *pdev->dev.dma_mask = dmamask; + pdev->dev.coherent_dma_mask = dmamask; + } + if (res) { ret = platform_device_add_resources(pdev, res, num_resources); if (ret) diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 9aa6f3ea9012..b391f4dcfcc2 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -1,29 +1,73 @@ -config IMX_HAVE_PLATFORM_ESDHC - bool - config IMX_HAVE_PLATFORM_FEC bool - default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51 + default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || ARCH_MX51 config IMX_HAVE_PLATFORM_FLEXCAN select HAVE_CAN_FLEXCAN if CAN bool +config IMX_HAVE_PLATFORM_FSL_USB2_UDC + bool + config IMX_HAVE_PLATFORM_GPIO_KEYS bool default y if ARCH_MX51 + +config IMX_HAVE_PLATFORM_IMX21_HCD + bool +config IMX_HAVE_PLATFORM_IMX2_WDT + bool + +config IMX_HAVE_PLATFORM_IMXDI_RTC + bool + +config IMX_HAVE_PLATFORM_IMX_FB + bool + select HAVE_FB_IMX + config IMX_HAVE_PLATFORM_IMX_I2C bool +config IMX_HAVE_PLATFORM_IMX_KEYPAD + bool + config IMX_HAVE_PLATFORM_IMX_SSI bool config IMX_HAVE_PLATFORM_IMX_UART bool +config IMX_HAVE_PLATFORM_IMX_UDC + bool + +config IMX_HAVE_PLATFORM_MX1_CAMERA + bool + +config IMX_HAVE_PLATFORM_MX2_CAMERA + bool + +config IMX_HAVE_PLATFORM_MXC_EHCI + bool + +config IMX_HAVE_PLATFORM_MXC_MMC + bool + config IMX_HAVE_PLATFORM_MXC_NAND bool +config IMX_HAVE_PLATFORM_MXC_PWM + bool + +config IMX_HAVE_PLATFORM_MXC_RNGA + bool + select ARCH_HAS_RNGA + +config IMX_HAVE_PLATFORM_MXC_W1 + bool + +config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + bool + config IMX_HAVE_PLATFORM_SPI_IMX bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 45aefeb283ba..75cd2ece9053 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -1,10 +1,24 @@ -obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o obj-y += platform-imx-dma.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c deleted file mode 100644 index 2605bfa0dfb0..000000000000 --- a/arch/arm/plat-mxc/devices/platform-esdhc.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include <mach/hardware.h> -#include <mach/devices-common.h> -#include <mach/esdhc.h> - -#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \ - { \ - .id = _id, \ - .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ - .irq = soc ## _INT_ESDHC ## hwid, \ - } - -#define imx_esdhc_imx_data_entry(soc, id, hwid) \ - [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid) - -#ifdef CONFIG_ARCH_MX25 -const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = { -#define imx25_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX25, _id, _hwid) - imx25_esdhc_data_entry(0, 1), - imx25_esdhc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_ARCH_MX25 */ - -#ifdef CONFIG_ARCH_MX35 -const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = { -#define imx35_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX35, _id, _hwid) - imx35_esdhc_data_entry(0, 1), - imx35_esdhc_data_entry(1, 2), - imx35_esdhc_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_ARCH_MX35 */ - -#ifdef CONFIG_ARCH_MX51 -const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = { -#define imx51_esdhc_data_entry(_id, _hwid) \ - imx_esdhc_imx_data_entry(MX51, _id, _hwid) - imx51_esdhc_data_entry(0, 1), - imx51_esdhc_data_entry(1, 2), - imx51_esdhc_data_entry(2, 3), - imx51_esdhc_data_entry(3, 4), -}; -#endif /* ifdef CONFIG_ARCH_MX51 */ - -struct platform_device *__init imx_add_esdhc( - const struct imx_esdhc_imx_data *data, - const struct esdhc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 11d087f4e219..8d78aedf8a93 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -16,17 +16,17 @@ .irq = soc ## _INT_FEC, \ } -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_fec_data imx25_fec_data __initconst = imx_fec_data_entry_single(MX25); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_fec_data imx27_fec_data __initconst = imx_fec_data_entry_single(MX27); #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_fec_data imx35_fec_data __initconst = imx_fec_data_entry_single(MX35); #endif diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c index 5e97a01f14f3..4e8497af2eb1 100644 --- a/arch/arm/plat-mxc/devices/platform-flexcan.c +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c @@ -5,26 +5,54 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ - +#include <mach/hardware.h> #include <mach/devices-common.h> -struct platform_device *__init imx_add_flexcan(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CAN ## _hwid, \ + } + +#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX25 +const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { +#define imx25_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_flexcan_data_entry(0, 1), + imx25_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { +#define imx35_flexcan_data_entry(_id, _hwid) \ + imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K) + imx35_flexcan_data_entry(0, 1), + imx35_flexcan_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, const struct flexcan_platform_data *pdata) { struct resource res[] = { { - .start = iobase, - .end = iobase + iosize - 1, + .start = data->iobase, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = irq, - .end = irq, + .start = data->irq, + .end = data->irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); + return imx_add_platform_device("flexcan", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c new file mode 100644 index 000000000000..59c33f6e401c --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_fsl_usb2_udc_data_entry_single(soc) \ + { \ + .iobase = soc ## _USB_OTG_BASE_ADDR, \ + .irq = soc ## _INT_USB_OTG, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = + imx_fsl_usb2_udc_data_entry_single(MX35); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("fsl-usb2-udc", -1, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 02d989018059..10f41ccf4146 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -39,20 +39,20 @@ struct imx_imx_sdma_data { }, \ } -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = @@ -94,20 +94,20 @@ static int __init imxXX_add_imx_dma(void) else #endif -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) ret = imx_add_imx_sdma(&imx25_imx_sdma_data); else #endif -#if defined(CONFIG_ARCH_MX31) +#if defined(CONFIG_SOC_IMX31) if (cpu_is_mx31()) { imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; ret = imx_add_imx_sdma(&imx31_imx_sdma_data); } else #endif -#if defined(CONFIG_ARCH_MX35) +#if defined(CONFIG_SOC_IMX35) if (cpu_is_mx35()) { imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; ret = imx_add_imx_sdma(&imx35_imx_sdma_data); diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c new file mode 100644 index 000000000000..6100a7d824dd --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_fb_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _LCDC_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_LCDC, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_fb_data imx21_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX21, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_fb_data imx25_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_fb_data imx27_imx_fb_data __initconst = + imx_imx_fb_data_entry_single(MX27, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx-fb", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 679588453aad..075bd8e337f8 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { #define imx25_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) @@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { imx25_imx_i2c_data_entry(1, 2), imx25_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { @@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { #define imx31_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) @@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { imx31_imx_i2c_data_entry(1, 2), imx31_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { #define imx35_imx_i2c_data_entry(_id, _hwid) \ imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) @@ -67,7 +67,7 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { imx35_imx_i2c_data_entry(1, 2), imx35_imx_i2c_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c new file mode 100644 index 000000000000..40238f0b8643 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_keypad_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _KPP_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_KPP, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX21, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX27, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX31, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = + imx_imx_keypad_data_entry_single(MX35, SZ_16); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx-keypad", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index 38a7a0b8f2f1..02002fc9ea24 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { #define imx25_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) imx25_imx_ssi_data_entry(0, 1), imx25_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { @@ -48,23 +48,23 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { #define imx31_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) imx31_imx_ssi_data_entry(0, 1), imx31_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { #define imx35_imx_ssi_data_entry(_id, _hwid) \ imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) imx35_imx_ssi_data_entry(0, 1), imx35_imx_ssi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 2039640adf27..08bbd65ee019 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { }; #endif -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { #define imx25_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) @@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { imx25_imx_uart_data_entry(3, 4), imx25_imx_uart_data_entry(4, 5), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { @@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { #define imx31_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) @@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { imx31_imx_uart_data_entry(3, 4), imx31_imx_uart_data_entry(4, 5), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { #define imx35_imx_uart_data_entry(_id, _hwid) \ imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) @@ -92,7 +92,7 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { imx35_imx_uart_data_entry(1, 2), imx35_imx_uart_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c new file mode 100644 index 000000000000..c61bd4e63149 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx2_wdt_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _WDOG_BASE_ADDR, \ + .iosize = _size, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX21, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX25, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX27, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX31, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = + imx_imx2_wdt_data_entry_single(MX35, SZ_16K); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, + }; + return imx_add_platform_device("imx2-wdt", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c new file mode 100644 index 000000000000..5770a42f33bf --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx21_hcd_data_entry_single(soc) \ + { \ + .iobase = soc ## _USBOTG_BASE_ADDR, \ + .irq = soc ## _INT_USBHOST, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst = + imx_imx21_hcd_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_8K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("imx21-hcd", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c new file mode 100644 index 000000000000..6fd675dfce14 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imx_udc_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _USBD_BASE_ADDR, \ + .iosize = _size, \ + .irq0 = soc ## _INT_USBD0, \ + .irq1 = soc ## _INT_USBD1, \ + .irq2 = soc ## _INT_USBD2, \ + .irq3 = soc ## _INT_USBD3, \ + .irq4 = soc ## _INT_USBD4, \ + .irq5 = soc ## _INT_USBD5, \ + .irq6 = soc ## _INT_USBD6, \ + } + +#define imx_imx_udc_data_entry(soc, _size) \ + [_id] = imx_imx_udc_data_entry_single(soc, _size) + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_udc_data imx1_imx_udc_data __initconst = + imx_imx_udc_data_entry_single(MX1, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq0, + .end = data->irq0, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq1, + .end = data->irq1, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq2, + .end = data->irq2, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq3, + .end = data->irq3, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq4, + .end = data->irq4, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq5, + .end = data->irq5, + .flags = IORESOURCE_IRQ, + }, { + .start = data->irq6, + .end = data->irq6, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imx_udc", 0, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c new file mode 100644 index 000000000000..10653cc8d1fa --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_imxdi_rtc_data_entry_single(soc) \ + { \ + .iobase = soc ## _DRYICE_BASE_ADDR, \ + .irq = soc ## _INT_DRYICE, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = + imx_imxdi_rtc_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("imxdi_rtc", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c new file mode 100644 index 000000000000..edcc581a30a9 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mx1_camera_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _CSI ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_CSI, \ + } + +#ifdef CONFIG_SOC_IMX1 +const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst = + imx_mx1_camera_data_entry_single(MX1, 10); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx1-camera", 0, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c new file mode 100644 index 000000000000..b3f4828dc447 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mx2_camera_data_entry_single(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_4K, \ + .irqcsi = soc ## _INT_CSI, \ + } +#define imx_mx2_camera_data_entry_single_emma(soc) \ + { \ + .iobasecsi = soc ## _CSI_BASE_ADDR, \ + .iosizecsi = SZ_32, \ + .irqcsi = soc ## _INT_CSI, \ + .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ + .iosizeemmaprp = SZ_32, \ + .irqemmaprp = soc ## _INT_EMMAPRP, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single(MX25); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = + imx_mx2_camera_data_entry_single_emma(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobasecsi, + .end = data->iobasecsi + data->iosizecsi - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqcsi, + .end = data->irqcsi, + .flags = IORESOURCE_IRQ, + }, { + .start = data->iobaseemmaprp, + .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irqemmaprp, + .end = data->irqemmaprp, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mx2-camera", 0, + res, data->iobaseemmaprp ? 4 : 2, + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c new file mode 100644 index 000000000000..cc488f4b6204 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \ + { \ + .id = _id, \ + .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \ + .irq = soc ## _INT_USB_ ## hs, \ + } + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 0, OTG); +const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX25, 1, HS); +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX27, 0, OTG); +const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX27, 1, HS1), + imx_mxc_ehci_data_entry_single(MX27, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX31, 0, OTG); +const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX31, 1, HS1), + imx_mxc_ehci_data_entry_single(MX31, 2, HS2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 0, OTG); +const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = + imx_mxc_ehci_data_entry_single(MX35, 1, HS); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + return imx_add_platform_device_dmamask("mxc-ehci", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c new file mode 100644 index 000000000000..90d762f6f93b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_SDHC ## _hwid, \ + .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ + } +#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { +#define imx21_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K) + imx21_mxc_mmc_data_entry(0, 1), + imx21_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { +#define imx27_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_mxc_mmc_data_entry(0, 1), + imx27_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = { +#define imx31_mxc_mmc_data_entry(_id, _hwid) \ + imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K) + imx31_mxc_mmc_data_entry(0, 1), + imx31_mxc_mmc_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX31 */ + +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, { + .start = data->dmareq, + .end = data->dmareq, + .flags = IORESOURCE_DMA, + }, + }; + return imx_add_platform_device_dmamask("mxc-mmc", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 3fdcc32e3d67..f5beac0cdde7 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -31,22 +31,22 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX21, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX21 */ -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX25, SZ_8K); -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX27, SZ_4K); #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX31, SZ_4K); #endif -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX35, SZ_8K); #endif diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c new file mode 100644 index 000000000000..3d8ebdba38ee --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2009-2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_PWM ## _hwid, \ + } +#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX25 +const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { +#define imx25_mxc_pwm_data_entry(_id, _hwid) \ + imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_mxc_pwm_data_entry(0, 1), + imx25_mxc_pwm_data_entry(1, 2), + imx25_mxc_pwm_data_entry(2, 3), + imx25_mxc_pwm_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = + imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("mxc_pwm", data->id, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c new file mode 100644 index 000000000000..b4b7612b6e17 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +struct imx_mxc_rnga_data { + resource_size_t iobase; +}; + +#define imx_mxc_rnga_data_entry_single(soc) \ + { \ + .iobase = soc ## _RNGA_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX31 +static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst = + imx_mxc_rnga_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +static struct platform_device *__init imx_add_mxc_rnga( + const struct imx_mxc_rnga_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + }; + return imx_add_platform_device("mxc_rnga", -1, + res, ARRAY_SIZE(res), NULL, 0); +} + +static int __init imxXX_add_mxc_rnga(void) +{ + struct platform_device *ret; + +#if defined(CONFIG_SOC_IMX31) + if (cpu_is_mx31()) + ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data); + else +#endif /* if defined(CONFIG_SOC_IMX31) */ + ret = ERR_PTR(-ENODEV); + + if (IS_ERR(ret)) + return PTR_ERR(ret); + + return 0; +} +arch_initcall(imxXX_add_mxc_rnga); diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c new file mode 100644 index 000000000000..96fa5ea91fe8 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_mxc_w1_data_entry_single(soc) \ + { \ + .iobase = soc ## _OWIRE_BASE_ADDR, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX21); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX27); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_SOC_IMX31 +const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX31); +#endif /* ifdef CONFIG_SOC_IMX31 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = + imx_mxc_w1_data_entry_single(MX35); +#endif /* ifdef CONFIG_SOC_IMX35 */ + +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + }; + + return imx_add_platform_device("mxc_w1", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c new file mode 100644 index 000000000000..167cce89e7c7 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ + +#include <mach/hardware.h> +#include <mach/devices-common.h> +#include <mach/esdhc.h> + +#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \ + { \ + .id = _id, \ + .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ + .irq = soc ## _INT_ESDHC ## hwid, \ + } + +#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \ + [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid) + +#ifdef CONFIG_SOC_IMX25 +const struct imx_sdhci_esdhc_imx_data +imx25_sdhci_esdhc_imx_data[] __initconst = { +#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid) + imx25_sdhci_esdhc_imx_data_entry(0, 1), + imx25_sdhci_esdhc_imx_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX25 */ + +#ifdef CONFIG_SOC_IMX35 +const struct imx_sdhci_esdhc_imx_data +imx35_sdhci_esdhc_imx_data[] __initconst = { +#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid) + imx35_sdhci_esdhc_imx_data_entry(0, 1), + imx35_sdhci_esdhc_imx_data_entry(1, 2), + imx35_sdhci_esdhc_imx_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX35 */ + +#ifdef CONFIG_ARCH_MX51 +const struct imx_sdhci_esdhc_imx_data +imx51_sdhci_esdhc_imx_data[] __initconst = { +#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ + imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid) + imx51_sdhci_esdhc_imx_data_entry(0, 1), + imx51_sdhci_esdhc_imx_data_entry(1, 2), + imx51_sdhci_esdhc_imx_data_entry(2, 3), + imx51_sdhci_esdhc_imx_data_entry(3, 4), +}; +#endif /* ifdef CONFIG_ARCH_MX51 */ + +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, + const struct esdhc_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, + ARRAY_SIZE(res), pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index e48340ec331e..8f2b60a6396e 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -29,7 +29,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { imx21_cspi_data_entry(1, 2), #endif -#ifdef CONFIG_ARCH_MX25 +#ifdef CONFIG_SOC_IMX25 const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { #define imx25_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) @@ -37,7 +37,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { imx25_cspi_data_entry(1, 2), imx25_cspi_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX25 */ +#endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { @@ -49,7 +49,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { }; #endif /* ifdef CONFIG_SOC_IMX27 */ -#ifdef CONFIG_ARCH_MX31 +#ifdef CONFIG_SOC_IMX31 const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { #define imx31_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) @@ -57,16 +57,16 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { imx31_cspi_data_entry(1, 2), imx31_cspi_data_entry(2, 3), }; -#endif /* ifdef CONFIG_ARCH_MX31 */ +#endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_ARCH_MX35 +#ifdef CONFIG_SOC_IMX35 const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { #define imx35_cspi_data_entry(_id, _hwid) \ imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) imx35_cspi_data_entry(0, 1), imx35_cspi_data_entry(1, 2), }; -#endif /* ifdef CONFIG_ARCH_MX35 */ +#endif /* ifdef CONFIG_SOC_IMX35 */ #ifdef CONFIG_ARCH_MX51 const struct imx_spi_imx_data imx51_cspi_data __initconst = diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 9915607683de..4bac3d5545d3 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -69,9 +69,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; -#if defined(CONFIG_ARCH_MX25) +#if defined(CONFIG_SOC_IMX25) if (cpu_is_mx25()) { - v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -108,11 +108,11 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) return -EINVAL; } - writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + + writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } -#endif /* CONFIG_ARCH_MX25 */ +#endif /* if defined(CONFIG_SOC_IMX25) */ #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 9c3e36232b5b..93a8d93dcc2e 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) { u32 irq_stat; - struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); + struct mxc_gpio_port *port = get_irq_data(irq); irq_stat = __raw_readl(port->base + GPIO_ISR) & __raw_readl(port->base + GPIO_IMR); @@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) { int i; u32 irq_msk, irq_stat; - struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); + struct mxc_gpio_port *port = get_irq_data(irq); /* walk through all interrupt status registers */ for (i = 0; i < gpio_table_size; i++) { @@ -349,3 +349,96 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) return 0; } + +#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ + { \ + .chip.label = "gpio-" #_id, \ + .irq = _irq, \ + .base = soc ## _IO_ADDRESS( \ + soc ## _GPIO ## _hwid ## _BASE_ADDR), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ + } + +#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ + DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) + +#define DEFINE_REGISTER_FUNCTION(prefix) \ +int __init prefix ## _register_gpios(void) \ +{ \ + return mxc_gpio_init(prefix ## _gpio_ports, \ + ARRAY_SIZE(prefix ## _gpio_ports)); \ +} + +#if defined(CONFIG_SOC_IMX1) +static struct mxc_gpio_port imx1_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC), + DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD), +}; + +DEFINE_REGISTER_FUNCTION(imx1) + +#endif /* if defined(CONFIG_SOC_IMX1) */ + +#if defined(CONFIG_SOC_IMX21) +static struct mxc_gpio_port imx21_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX21, 1, 2), + DEFINE_IMX_GPIO_PORT(MX21, 2, 3), + DEFINE_IMX_GPIO_PORT(MX21, 3, 4), + DEFINE_IMX_GPIO_PORT(MX21, 4, 5), + DEFINE_IMX_GPIO_PORT(MX21, 5, 6), +}; + +DEFINE_REGISTER_FUNCTION(imx21) + +#endif /* if defined(CONFIG_SOC_IMX21) */ + +#if defined(CONFIG_SOC_IMX25) +static struct mxc_gpio_port imx25_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3), + DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4), +}; + +DEFINE_REGISTER_FUNCTION(imx25) + +#endif /* if defined(CONFIG_SOC_IMX25) */ + +#if defined(CONFIG_SOC_IMX27) +static struct mxc_gpio_port imx27_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO), + DEFINE_IMX_GPIO_PORT(MX27, 1, 2), + DEFINE_IMX_GPIO_PORT(MX27, 2, 3), + DEFINE_IMX_GPIO_PORT(MX27, 3, 4), + DEFINE_IMX_GPIO_PORT(MX27, 4, 5), + DEFINE_IMX_GPIO_PORT(MX27, 5, 6), +}; + +DEFINE_REGISTER_FUNCTION(imx27) + +#endif /* if defined(CONFIG_SOC_IMX27) */ + +#if defined(CONFIG_SOC_IMX31) +static struct mxc_gpio_port imx31_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), +}; + +DEFINE_REGISTER_FUNCTION(imx31) + +#endif /* if defined(CONFIG_SOC_IMX31) */ + +#if defined(CONFIG_SOC_IMX35) +static struct mxc_gpio_port imx35_gpio_ports[] = { + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), + DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), +}; + +DEFINE_REGISTER_FUNCTION(imx35) + +#endif /* if defined(CONFIG_SOC_IMX35) */ diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index d56213fb901b..3b3a37c25c56 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -10,58 +10,49 @@ * published by the Free Software Foundation. * */ -#define IMX_NEEDS_DEPRECATED_SYMBOLS +#include <mach/hardware.h> #ifdef CONFIG_ARCH_MX1 -#include <mach/mx1.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX1_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX25 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx25.h> #define UART_PADDR MX25_UART1_BASE_ADDR -#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MX2 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx2x.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX2x_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX3 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx3x.h> -#define UART_PADDR UART1_BASE_ADDR -#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +#define UART_PADDR MX3x_UART1_BASE_ADDR #endif #ifdef CONFIG_ARCH_MX5 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mx51.h> #define UART_PADDR MX51_UART1_BASE_ADDR -#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) #endif #ifdef CONFIG_ARCH_MXC91231 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif -#include <mach/mxc91231.h> #define UART_PADDR MXC91231_UART2_BASE_ADDR -#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) #endif + +#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) + .macro addruart, rp, rv ldr \rp, =UART_PADDR @ physical ldr \rv, =UART_VADDR @ virtual diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 8c6896fd1e5f..3640eaf88c02 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -10,9 +10,19 @@ #include <linux/platform_device.h> #include <linux/init.h> -struct platform_device *imx_add_platform_device(const char *name, int id, +struct platform_device *imx_add_platform_device_dmamask( + const char *name, int id, const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data); + const void *data, size_t size_data, u64 dmamask); + +static inline struct platform_device *imx_add_platform_device( + const char *name, int id, + const struct resource *res, unsigned int num_resources, + const void *data, size_t size_data) +{ + return imx_add_platform_device_dmamask( + name, id, res, num_resources, data, size_data, 0); +} #include <linux/fec.h> struct imx_fec_data { @@ -24,15 +34,62 @@ struct platform_device *__init imx_add_fec( const struct fec_platform_data *pdata); #include <linux/can/platform/flexcan.h> -struct platform_device *__init imx_add_flexcan(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +struct imx_flexcan_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_flexcan( + const struct imx_flexcan_data *data, const struct flexcan_platform_data *pdata); +#include <linux/fsl_devices.h> +struct imx_fsl_usb2_udc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_fsl_usb2_udc( + const struct imx_fsl_usb2_udc_data *data, + const struct fsl_usb2_platform_data *pdata); + #include <linux/gpio_keys.h> struct platform_device *__init imx_add_gpio_keys( const struct gpio_keys_platform_data *pdata); +#include <mach/mx21-usbhost.h> +struct imx_imx21_hcd_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx21_hcd( + const struct imx_imx21_hcd_data *data, + const struct mx21_usbh_platform_data *pdata); + +struct imx_imx2_wdt_data { + resource_size_t iobase; + resource_size_t iosize; +}; +struct platform_device *__init imx_add_imx2_wdt( + const struct imx_imx2_wdt_data *data); + +struct imx_imxdi_rtc_data { + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imxdi_rtc( + const struct imx_imxdi_rtc_data *data); + +#include <mach/imxfb.h> +struct imx_imx_fb_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_fb( + const struct imx_imx_fb_data *data, + const struct imx_fb_platform_data *pdata); + #include <mach/i2c.h> struct imx_imx_i2c_data { int id; @@ -44,6 +101,16 @@ struct platform_device *__init imx_add_imx_i2c( const struct imx_imx_i2c_data *data, const struct imxi2c_platform_data *pdata); +#include <linux/input/matrix_keypad.h> +struct imx_imx_keypad_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_keypad( + const struct imx_imx_keypad_data *data, + const struct matrix_keymap_data *pdata); + #include <mach/ssi.h> struct imx_imx_ssi_data { int id; @@ -82,6 +149,67 @@ struct platform_device *__init imx_add_imx_uart_1irq( const struct imx_imx_uart_1irq_data *data, const struct imxuart_platform_data *pdata); +#include <mach/usb.h> +struct imx_imx_udc_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq0; + resource_size_t irq1; + resource_size_t irq2; + resource_size_t irq3; + resource_size_t irq4; + resource_size_t irq5; + resource_size_t irq6; +}; +struct platform_device *__init imx_add_imx_udc( + const struct imx_imx_udc_data *data, + const struct imxusb_platform_data *pdata); + +#include <mach/mx1_camera.h> +struct imx_mx1_camera_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mx1_camera( + const struct imx_mx1_camera_data *data, + const struct mx1_camera_pdata *pdata); + +#include <mach/mx2_cam.h> +struct imx_mx2_camera_data { + resource_size_t iobasecsi; + resource_size_t iosizecsi; + resource_size_t irqcsi; + resource_size_t iobaseemmaprp; + resource_size_t iosizeemmaprp; + resource_size_t irqemmaprp; +}; +struct platform_device *__init imx_add_mx2_camera( + const struct imx_mx2_camera_data *data, + const struct mx2_camera_platform_data *pdata); + +#include <mach/mxc_ehci.h> +struct imx_mxc_ehci_data { + int id; + resource_size_t iobase; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_ehci( + const struct imx_mxc_ehci_data *data, + const struct mxc_usbh_platform_data *pdata); + +#include <mach/mmc.h> +struct imx_mxc_mmc_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + resource_size_t dmareq; +}; +struct platform_device *__init imx_add_mxc_mmc( + const struct imx_mxc_mmc_data *data, + const struct imxmmc_platform_data *pdata); + #include <mach/mxc_nand.h> struct imx_mxc_nand_data { /* @@ -99,24 +227,39 @@ struct platform_device *__init imx_add_mxc_nand( const struct imx_mxc_nand_data *data, const struct mxc_nand_platform_data *pdata); -#include <mach/spi.h> -struct imx_spi_imx_data { - const char *devid; +struct imx_mxc_pwm_data { int id; resource_size_t iobase; resource_size_t iosize; - int irq; + resource_size_t irq; }; -struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, - const struct spi_imx_master *pdata); +struct platform_device *__init imx_add_mxc_pwm( + const struct imx_mxc_pwm_data *data); + +struct imx_mxc_w1_data { + resource_size_t iobase; +}; +struct platform_device *__init imx_add_mxc_w1( + const struct imx_mxc_w1_data *data); #include <mach/esdhc.h> -struct imx_esdhc_imx_data { +struct imx_sdhci_esdhc_imx_data { int id; resource_size_t iobase; resource_size_t irq; }; -struct platform_device *__init imx_add_esdhc( - const struct imx_esdhc_imx_data *data, +struct platform_device *__init imx_add_sdhci_esdhc_imx( + const struct imx_sdhci_esdhc_imx_data *data, const struct esdhc_platform_data *pdata); + +#include <mach/spi.h> +struct imx_spi_imx_data { + const char *devid; + int id; + resource_size_t iobase; + resource_size_t iosize; + int irq; +}; +struct platform_device *__init imx_add_spi_imx( + const struct imx_spi_imx_data *data, + const struct spi_imx_master *pdata); diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index ebadf4ac43fc..dde777c10176 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -22,10 +22,82 @@ #include <asm/sizes.h> -#define IMX_IO_ADDRESS(addr, module) \ - ((void __force __iomem *) \ - (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ - (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) +#ifdef __ASSEMBLER__ +#define IOMEM(addr) (addr) +#else +#define IOMEM(addr) ((void __force __iomem *)(addr)) +#endif + +#define IMX_IO_P2V_MODULE(addr, module) \ + (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ + (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) + +/* + * This is rather complicated for humans and ugly to verify, but for a machine + * it's OK. Still more as it is usually only applied to constants. The upsides + * on using this approach are: + * + * - same mapping on all i.MX machines + * - works for assembler, too + * - no need to nurture #defines for virtual addresses + * + * The downside it, it's hard to verify (but I have a script for that). + * + * Obviously this needs to be injective for each SoC. In general it maps the + * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff] + * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there). + * + * It applies the following mappings for the different SoCs: + * + * mx1: + * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 + * mx21: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 + * mx25: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * mx27: + * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 + * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 + * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 + * mx31: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx35: + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * mx51: + * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 + * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 + * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 + * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 + * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 + * mxc91231: + * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000 + * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 + * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000 + * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000 + * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 + * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 + * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000 + * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 + */ +#define IMX_IO_P2V(x) ( \ + 0xf4000000 + \ + (((x) & 0x50000000) >> 6) + \ + (((x) & 0x0b000000) >> 4) + \ + (((x) & 0x000fffff))) + +#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) #ifdef CONFIG_ARCH_MX5 #include <mach/mx51.h> @@ -61,4 +133,11 @@ #include <mach/mxc.h> +#define imx_map_entry(soc, name, _type) { \ + .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ + .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ + .length = soc ## _ ## name ## _SIZE, \ + .type = _type, \ +} + #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 5263506b7ddf..9de8f062ad5d 100644 --- a/arch/arm/plat-mxc/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h @@ -1,6 +1,8 @@ /* * This structure describes the machine which we are running on. */ +#ifndef __MACH_IMXFB_H__ +#define __MACH_IMXFB_H__ #include <linux/fb.h> @@ -79,3 +81,4 @@ struct imx_fb_platform_data { }; void set_imx_fb_info(struct imx_fb_platform_data *); +#endif /* ifndef __MACH_IMXFB_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 641b24618239..75d96214b831 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -19,7 +19,6 @@ */ #define MX1_IO_BASE_ADDR 0x00200000 #define MX1_IO_SIZE SZ_1M -#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END #define MX1_CS0_PHYS 0x10000000 #define MX1_CS0_SIZE 0x02000000 @@ -66,6 +65,10 @@ #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) +#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) +#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) @@ -73,12 +76,12 @@ #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) /* macro to get at IO space when running virtually */ -#define MX1_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX1_IO)) +#define MX1_IO_P2V(x) IMX_IO_P2V(x) +#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) /* fixed interrput numbers */ #define MX1_INT_SOFTINT 0 -#define MX1_CSI_INT 6 +#define MX1_INT_CSI 6 #define MX1_DSPA_MAC_INT 7 #define MX1_DSPA_INT 8 #define MX1_COMP_INT 9 @@ -115,13 +118,13 @@ #define MX1_SSI_RX_INT 44 #define MX1_SSI_RX_ERR_INT 45 #define MX1_TOUCH_INT 46 -#define MX1_USBD_INT0 47 -#define MX1_USBD_INT1 48 -#define MX1_USBD_INT2 49 -#define MX1_USBD_INT3 50 -#define MX1_USBD_INT4 51 -#define MX1_USBD_INT5 52 -#define MX1_USBD_INT6 53 +#define MX1_INT_USBD0 47 +#define MX1_INT_USBD1 48 +#define MX1_INT_USBD2 49 +#define MX1_INT_USBD3 50 +#define MX1_INT_USBD4 51 +#define MX1_INT_USBD5 52 +#define MX1_INT_USBD6 53 #define MX1_BTSYS_INT 55 #define MX1_BTTIM_INT 56 #define MX1_BTWUI_INT 57 @@ -164,134 +167,6 @@ * to not break drivers/usb/gadget/imx_udc. Should go * away after this driver uses the new name. */ -#define USBD_INT0 MX1_USBD_INT0 - -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define IMX_IO_PHYS MX1_IO_BASE_ADDR -#define IMX_IO_SIZE MX1_IO_SIZE -#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT -#define IMX_CS0_PHYS MX1_CS0_PHYS -#define IMX_CS0_SIZE MX1_CS0_SIZE -#define IMX_CS1_PHYS MX1_CS1_PHYS -#define IMX_CS1_SIZE MX1_CS1_SIZE -#define IMX_CS2_PHYS MX1_CS2_PHYS -#define IMX_CS2_SIZE MX1_CS2_SIZE -#define IMX_CS3_PHYS MX1_CS3_PHYS -#define IMX_CS3_SIZE MX1_CS3_SIZE -#define IMX_CS4_PHYS MX1_CS4_PHYS -#define IMX_CS4_SIZE MX1_CS4_SIZE -#define IMX_CS5_PHYS MX1_CS5_PHYS -#define IMX_CS5_SIZE MX1_CS5_SIZE -#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR -#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR -#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR -#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR -#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR -#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR -#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR -#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR -#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR -#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR -#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR -#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR -#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR -#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR -#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR -#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR -#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR -#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR -#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR -#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR -#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR -#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR -#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR -#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR -#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR -#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR -#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR -#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR -#define IO_ADDRESS(x) MX1_IO_ADDRESS(x) -#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) -#define INT_SOFTINT MX1_INT_SOFTINT -#define CSI_INT MX1_CSI_INT -#define DSPA_MAC_INT MX1_DSPA_MAC_INT -#define DSPA_INT MX1_DSPA_INT -#define COMP_INT MX1_COMP_INT -#define MSHC_XINT MX1_MSHC_XINT -#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA -#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB -#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC -#define LCDC_INT MX1_LCDC_INT -#define SIM_INT MX1_SIM_INT -#define SIM_DATA_INT MX1_SIM_DATA_INT -#define RTC_INT MX1_RTC_INT -#define RTC_SAMINT MX1_RTC_SAMINT -#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR -#define UART2_MINT_RTS MX1_UART2_MINT_RTS -#define UART2_MINT_DTR MX1_UART2_MINT_DTR -#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC -#define UART2_MINT_TX MX1_UART2_MINT_TX -#define UART2_MINT_RX MX1_UART2_MINT_RX -#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR -#define UART1_MINT_RTS MX1_UART1_MINT_RTS -#define UART1_MINT_DTR MX1_UART1_MINT_DTR -#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC -#define UART1_MINT_TX MX1_UART1_MINT_TX -#define UART1_MINT_RX MX1_UART1_MINT_RX -#define VOICE_DAC_INT MX1_VOICE_DAC_INT -#define VOICE_ADC_INT MX1_VOICE_ADC_INT -#define PEN_DATA_INT MX1_PEN_DATA_INT -#define PWM_INT MX1_PWM_INT -#define SDHC_INT MX1_SDHC_INT -#define I2C_INT MX1_INT_I2C -#define CSPI_INT MX1_CSPI_INT -#define SSI_TX_INT MX1_SSI_TX_INT -#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT -#define SSI_RX_INT MX1_SSI_RX_INT -#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT -#define TOUCH_INT MX1_TOUCH_INT -#define USBD_INT1 MX1_USBD_INT1 -#define USBD_INT2 MX1_USBD_INT2 -#define USBD_INT3 MX1_USBD_INT3 -#define USBD_INT4 MX1_USBD_INT4 -#define USBD_INT5 MX1_USBD_INT5 -#define USBD_INT6 MX1_USBD_INT6 -#define BTSYS_INT MX1_BTSYS_INT -#define BTTIM_INT MX1_BTTIM_INT -#define BTWUI_INT MX1_BTWUI_INT -#define TIM2_INT MX1_TIM2_INT -#define TIM1_INT MX1_TIM1_INT -#define DMA_ERR MX1_DMA_ERR -#define DMA_INT MX1_DMA_INT -#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD -#define WDT_INT MX1_WDT_INT -#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T -#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R -#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T -#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R -#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT -#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R -#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC -#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT -#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN -#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC -#define DMA_REQ_EXT MX1_DMA_REQ_EXT -#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC -#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R -#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T -#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T -#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R -#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC -#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC -#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) -#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R -#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T -#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T -#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R -#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T -#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R -#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ +#define USBD_INT0 MX1_INT_USBD0 #endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 8bc59720b6e4..6cd049ebbd8d 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -26,7 +26,6 @@ #define __MACH_MX21_H__ #define MX21_AIPI_BASE_ADDR 0x10000000 -#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX21_AIPI_SIZE SZ_1M #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) @@ -49,6 +48,12 @@ #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) +#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) +#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) +#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) +#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) +#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) +#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) @@ -64,7 +69,6 @@ #define MX21_AVIC_BASE_ADDR 0x10040000 #define MX21_SAHB1_BASE_ADDR 0x80000000 -#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX21_SAHB1_SIZE SZ_1M #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) @@ -82,7 +86,6 @@ /* NAND, SDRAM, WEIM etc controllers */ #define MX21_X_MEMC_BASE_ADDR 0xdf000000 -#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000 #define MX21_X_MEMC_SIZE SZ_256K #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) @@ -92,10 +95,8 @@ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ -#define MX21_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ - IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \ - IMX_IO_ADDRESS(x, MX21_X_MEMC)) +#define MX21_IO_P2V(x) IMX_IO_P2V(x) +#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) /* fixed interrupt numbers */ #define MX21_INT_CSPI3 6 @@ -184,39 +185,4 @@ #define MX21_DMA_REQ_CSI_STAT 30 #define MX21_DMA_REQ_CSI_RX 31 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR -#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR -#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR -#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX21_X_MEMC_SIZE -#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR -#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR -#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR -#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR -#define MXC_INT_FIRI MX21_INT_FIRI -#define MXC_INT_BMI MX21_INT_BMI -#define MXC_INT_EMMAENC MX21_INT_EMMAENC -#define MXC_INT_EMMADEC MX21_INT_EMMADEC -#define MXC_INT_USBWKUP MX21_INT_USBWKUP -#define MXC_INT_USBDMA MX21_INT_USBDMA -#define MXC_INT_USBHOST MX21_INT_USBHOST -#define MXC_INT_USBFUNC MX21_INT_USBFUNC -#define MXC_INT_USBMNP MX21_INT_USBMNP -#define MXC_INT_USBCTRL MX21_INT_USBCTRL -#define MXC_INT_USBCTRL MX21_INT_USBCTRL -#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX -#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX -#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX -#endif - #endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index cf46a45b0d4e..024bebe4da11 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -2,13 +2,10 @@ #define __MACH_MX25_H__ #define MX25_AIPS1_BASE_ADDR 0x43f00000 -#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX25_AIPS1_SIZE SZ_1M #define MX25_AIPS2_BASE_ADDR 0x53f00000 -#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX25_AIPS2_SIZE SZ_1M #define MX25_AVIC_BASE_ADDR 0x68000000 -#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) @@ -21,20 +18,15 @@ #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) +#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) +#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) +#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) +#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) +#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) +#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) +#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) - -#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) -#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) -#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) -#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) - -#define MX25_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX25_AVIC)) - -#define MX25_AIPS1_IO_ADDRESS(x) \ - (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) +#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) #define MX25_UART1_BASE_ADDR 0x43f90000 #define MX25_UART2_BASE_ADDR 0x43f94000 @@ -55,9 +47,14 @@ #define MX25_LCDC_BASE_ADDR 0x53fbc000 #define MX25_KPP_BASE_ADDR 0x43fa8000 #define MX25_SDMA_BASE_ADDR 0x53fd4000 -#define MX25_OTG_BASE_ADDR 0x53ff4000 +#define MX25_USB_BASE_ADDR 0x53ff4000 +#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) +#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0200) #define MX25_CSI_BASE_ADDR 0x53ff8000 +#define MX25_IO_P2V(x) IMX_IO_P2V(x) +#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) + #define MX25_INT_CSPI3 0 #define MX25_INT_I2C1 3 #define MX25_INT_I2C2 4 @@ -69,18 +66,28 @@ #define MX25_INT_SSI1 12 #define MX25_INT_CSPI2 13 #define MX25_INT_CSPI1 14 +#define MX25_INT_GPIO3 16 #define MX25_INT_CSI 17 #define MX25_INT_UART3 18 +#define MX25_INT_GPIO4 23 #define MX25_INT_KPP 24 #define MX25_INT_DRYICE 25 +#define MX25_INT_PWM1 26 #define MX25_INT_UART2 32 #define MX25_INT_NFC 33 #define MX25_INT_SDMA 34 +#define MX25_INT_USB_HS 35 +#define MX25_INT_PWM2 36 +#define MX25_INT_USB_OTG 37 #define MX25_INT_LCDC 39 #define MX25_INT_UART5 40 +#define MX25_INT_PWM3 41 +#define MX25_INT_PWM4 42 #define MX25_INT_CAN1 43 #define MX25_INT_CAN2 44 #define MX25_INT_UART1 45 +#define MX25_INT_GPIO2 51 +#define MX25_INT_GPIO1 52 #define MX25_INT_FEC 57 #define MX25_DMA_REQ_SSI2_RX1 22 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 2237ba2e5351..eb09ec09dbe5 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -29,7 +29,6 @@ #endif #define MX27_AIPI_BASE_ADDR 0x10000000 -#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX27_AIPI_SIZE SZ_1M #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) @@ -52,6 +51,12 @@ #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) +#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) +#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) +#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) +#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) +#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) +#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) @@ -65,11 +70,13 @@ #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) -#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) -#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR +#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) +#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) +#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) +#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) -#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) -#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) +#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) +#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) @@ -87,7 +94,6 @@ #define MX27_ROMP_BASE_ADDR 0x10041000 #define MX27_SAHB1_BASE_ADDR 0x80000000 -#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX27_SAHB1_SIZE SZ_1M #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) @@ -105,7 +111,6 @@ /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX27_X_MEMC_BASE_ADDR 0xd8000000 -#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 #define MX27_X_MEMC_SIZE SZ_1M #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) @@ -123,10 +128,8 @@ /* IRAM */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ -#define MX27_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ - IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ - IMX_IO_ADDRESS(x, MX27_X_MEMC)) +#define MX27_IO_P2V(x) IMX_IO_P2V(x) +#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) #ifndef __ASSEMBLER__ static inline void mx27_setup_weimcs(size_t cs, @@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_EMMAPRP 51 #define MX27_INT_EMMAPP 52 #define MX27_INT_VPU 53 -#define MX27_INT_USB1 54 -#define MX27_INT_USB2 55 -#define MX27_INT_USB3 56 +#define MX27_INT_USB_HS1 54 +#define MX27_INT_USB_HS2 55 +#define MX27_INT_USB_OTG 56 #define MX27_INT_SCC_SMN 57 #define MX27_INT_SCC_SCM 58 #define MX27_INT_SAHARA 59 @@ -249,74 +252,4 @@ static inline void mx27_setup_weimcs(size_t cs, extern int mx27_revision(void); #endif -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR -#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR -#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR -#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR -#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR -#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR -#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR -#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR -#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR -#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR -#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR -#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR -#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR -#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR -#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR -#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR -#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR -#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR -#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR -#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR -#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR -#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR -#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX27_X_MEMC_SIZE -#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR -#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR -#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR -#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR -#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR -#define MXC_INT_I2C2 MX27_INT_I2C2 -#define MXC_INT_GPT6 MX27_INT_GPT6 -#define MXC_INT_GPT5 MX27_INT_GPT5 -#define MXC_INT_GPT4 MX27_INT_GPT4 -#define MXC_INT_RTIC MX27_INT_RTIC -#define MXC_INT_SDHC MX27_INT_SDHC -#define MXC_INT_SDHC3 MX27_INT_SDHC3 -#define MXC_INT_ATA MX27_INT_ATA -#define MXC_INT_UART6 MX27_INT_UART6 -#define MXC_INT_UART5 MX27_INT_UART5 -#define MXC_INT_FEC MX27_INT_FEC -#define MXC_INT_VPU MX27_INT_VPU -#define MXC_INT_USB1 MX27_INT_USB1 -#define MXC_INT_USB2 MX27_INT_USB2 -#define MXC_INT_USB3 MX27_INT_USB3 -#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN -#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM -#define MXC_INT_SAHARA MX27_INT_SAHARA -#define MXC_INT_IIM MX27_INT_IIM -#define MXC_INT_CCM MX27_INT_CCM -#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC -#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX -#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV -#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX -#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX -#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX -#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX -#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 -#define DMA_REQ_NFC MX27_DMA_REQ_NFC -#endif - #endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index afb895a0b5b8..6d07839fdec2 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -27,7 +27,6 @@ /* Register offsets */ #define MX2x_AIPI_BASE_ADDR 0x10000000 -#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX2x_AIPI_SIZE SZ_1M #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) @@ -65,43 +64,9 @@ #define MX2x_AVIC_BASE_ADDR 0x10040000 #define MX2x_SAHB1_BASE_ADDR 0x80000000 -#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000 #define MX2x_SAHB1_SIZE SZ_1M #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) -/* - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ - AIPI_IO_ADDRESS(x) : \ - ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ - SAHB1_IO_ADDRESS(x) : \ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ - X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) - -/* define the address mapping macros: in physical address order */ -#define AIPI_IO_ADDRESS(x) \ - (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) - -#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) - -#define SAHB1_IO_ADDRESS(x) \ - (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) - -#define CS4_IO_ADDRESS(x) \ - (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) - -#define X_MEMC_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - -#define PCMCIA_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - /* fixed interrupt numbers */ #define MX2x_INT_CSPI3 6 #define MX2x_INT_GPIO 8 @@ -176,118 +141,4 @@ #define MX2x_DMA_REQ_CSI_STAT 30 #define MX2x_DMA_REQ_CSI_RX 31 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR -#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT -#define AIPI_SIZE MX2x_AIPI_SIZE -#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR -#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR -#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR -#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR -#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR -#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR -#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR -#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR -#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR -#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR -#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR -#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR -#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR -#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR -#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR -#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR -#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR -#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR -#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR -#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR -#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR -#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR -#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR -#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR -#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR -#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR -#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR -#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR -#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR -#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR -#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR -#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR -#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR -#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT -#define SAHB1_SIZE MX2x_SAHB1_SIZE -#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR -#define MXC_INT_CSPI3 MX2x_INT_CSPI3 -#define MXC_INT_GPIO MX2x_INT_GPIO -#define MXC_INT_SDHC2 MX2x_INT_SDHC2 -#define MXC_INT_SDHC1 MX2x_INT_SDHC1 -#define MXC_INT_I2C MX2x_INT_I2C -#define MXC_INT_SSI2 MX2x_INT_SSI2 -#define MXC_INT_SSI1 MX2x_INT_SSI1 -#define MXC_INT_CSPI2 MX2x_INT_CSPI2 -#define MXC_INT_CSPI1 MX2x_INT_CSPI1 -#define MXC_INT_UART4 MX2x_INT_UART4 -#define MXC_INT_UART3 MX2x_INT_UART3 -#define MXC_INT_UART2 MX2x_INT_UART2 -#define MXC_INT_UART1 MX2x_INT_UART1 -#define MXC_INT_KPP MX2x_INT_KPP -#define MXC_INT_RTC MX2x_INT_RTC -#define MXC_INT_PWM MX2x_INT_PWM -#define MXC_INT_GPT3 MX2x_INT_GPT3 -#define MXC_INT_GPT2 MX2x_INT_GPT2 -#define MXC_INT_GPT1 MX2x_INT_GPT1 -#define MXC_INT_WDOG MX2x_INT_WDOG -#define MXC_INT_PCMCIA MX2x_INT_PCMCIA -#define MXC_INT_NANDFC MX2x_INT_NANDFC -#define MXC_INT_CSI MX2x_INT_CSI -#define MXC_INT_DMACH0 MX2x_INT_DMACH0 -#define MXC_INT_DMACH1 MX2x_INT_DMACH1 -#define MXC_INT_DMACH2 MX2x_INT_DMACH2 -#define MXC_INT_DMACH3 MX2x_INT_DMACH3 -#define MXC_INT_DMACH4 MX2x_INT_DMACH4 -#define MXC_INT_DMACH5 MX2x_INT_DMACH5 -#define MXC_INT_DMACH6 MX2x_INT_DMACH6 -#define MXC_INT_DMACH7 MX2x_INT_DMACH7 -#define MXC_INT_DMACH8 MX2x_INT_DMACH8 -#define MXC_INT_DMACH9 MX2x_INT_DMACH9 -#define MXC_INT_DMACH10 MX2x_INT_DMACH10 -#define MXC_INT_DMACH11 MX2x_INT_DMACH11 -#define MXC_INT_DMACH12 MX2x_INT_DMACH12 -#define MXC_INT_DMACH13 MX2x_INT_DMACH13 -#define MXC_INT_DMACH14 MX2x_INT_DMACH14 -#define MXC_INT_DMACH15 MX2x_INT_DMACH15 -#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP -#define MXC_INT_EMMAPP MX2x_INT_EMMAPP -#define MXC_INT_SLCDC MX2x_INT_SLCDC -#define MXC_INT_LCDC MX2x_INT_LCDC -#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX -#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX -#define DMA_REQ_EXT MX2x_DMA_REQ_EXT -#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2 -#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1 -#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0 -#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0 -#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1 -#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1 -#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0 -#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0 -#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1 -#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1 -#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX -#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX -#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX -#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX -#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX -#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX -#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX -#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX -#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX -#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX -#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX -#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX -#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT -#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX -#endif - #endif /* ifndef __MACH_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 61cfe827498b..092323144e2b 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -15,7 +15,6 @@ #define MX31_L2CC_SIZE SZ_1M #define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX31_AIPS1_SIZE SZ_1M #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) @@ -25,7 +24,10 @@ #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) -#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) +#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) +#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) @@ -41,10 +43,9 @@ #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) #define MX31_SPBA0_BASE_ADDR 0x50000000 -#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX31_SPBA0_SIZE SZ_1M -#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) -#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) +#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) +#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) @@ -55,7 +56,6 @@ #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) #define MX31_AIPS2_BASE_ADDR 0x53f00000 -#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX31_AIPS2_SIZE SZ_1M #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) @@ -84,7 +84,6 @@ #define MX31_ROMP_SIZE SZ_1M #define MX31_AVIC_BASE_ADDR 0x68000000 -#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX31_AVIC_SIZE SZ_1M #define MX31_IPU_MEM_BASE_ADDR 0x70000000 @@ -97,15 +96,14 @@ #define MX31_CS3_BASE_ADDR 0xb2000000 #define MX31_CS4_BASE_ADDR 0xb4000000 -#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX31_CS4_SIZE SZ_32M #define MX31_CS5_BASE_ADDR 0xb6000000 -#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX31_CS5_SIZE SZ_32M #define MX31_X_MEMC_BASE_ADDR 0xb8000000 -#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX31_X_MEMC_SIZE SZ_64K #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) @@ -121,12 +119,8 @@ #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX31_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX31_AVIC) ?: \ - IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MX31_SPBA0)) +#define MX31_IO_P2V(x) IMX_IO_P2V(x) +#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) #ifndef __ASSEMBLER__ static inline void mx31_setup_weimcs(size_t cs, @@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_MPEG4_ENCODER 5 #define MX31_INT_RTIC 6 #define MX31_INT_FIRI 7 -#define MX31_INT_MMC_SDHC2 8 -#define MX31_INT_MMC_SDHC1 9 +#define MX31_INT_SDHC2 8 +#define MX31_INT_SDHC1 9 #define MX31_INT_I2C1 10 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 @@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_UART2 32 #define MX31_INT_NFC 33 #define MX31_INT_SDMA 34 -#define MX31_INT_USB1 35 -#define MX31_INT_USB2 36 -#define MX31_INT_USB3 37 -#define MX31_INT_USB4 38 +#define MX31_INT_USB_HS1 35 +#define MX31_INT_USB_HS2 36 +#define MX31_INT_USB_OTG 37 #define MX31_INT_MSHC1 39 #define MX31_INT_MSHC2 40 #define MX31_INT_IPU_ERR 41 @@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_EXT_WDOG 62 #define MX31_INT_EXT_TV 63 +#define MX31_DMA_REQ_SDHC1 20 +#define MX31_DMA_REQ_SDHC2 21 #define MX31_DMA_REQ_SSI2_RX1 22 #define MX31_DMA_REQ_SSI2_TX1 23 #define MX31_DMA_REQ_SSI2_RX0 24 @@ -224,36 +219,4 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 #define MX31_SYSTEM_REV_NUM 3 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR -#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR -#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR -#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR -#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR -#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR -#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR -#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR -#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR -#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR -#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR -#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR -#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER -#define MXC_INT_FIRI MX31_INT_FIRI -#define MXC_INT_MBX MX31_INT_MBX -#define MXC_INT_CSPI3 MX31_INT_CSPI3 -#define MXC_INT_SIM2 MX31_INT_SIM2 -#define MXC_INT_SIM1 MX31_INT_SIM1 -#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS -#define MXC_INT_USB1 MX31_INT_USB1 -#define MXC_INT_USB2 MX31_INT_USB2 -#define MXC_INT_USB3 MX31_INT_USB3 -#define MXC_INT_USB4 MX31_INT_USB4 -#define MXC_INT_MSHC2 MX31_INT_MSHC2 -#define MXC_INT_UART4 MX31_INT_UART4 -#define MXC_INT_UART5 MX31_INT_UART5 -#define MXC_INT_CCM MX31_INT_CCM -#define MXC_INT_PCMCIA MX31_INT_PCMCIA -#endif - #endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 6267cff6035d..0fa3f6855349 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -11,7 +11,6 @@ #define MX35_L2CC_SIZE SZ_1M #define MX35_AIPS1_BASE_ADDR 0x43f00000 -#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX35_AIPS1_SIZE SZ_1M #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) @@ -33,7 +32,6 @@ #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) #define MX35_SPBA0_BASE_ADDR 0x50000000 -#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX35_SPBA0_SIZE SZ_1M #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) @@ -44,7 +42,6 @@ #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) #define MX35_AIPS2_BASE_ADDR 0x53f00000 -#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX35_AIPS2_SIZE SZ_1M #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) @@ -68,15 +65,19 @@ #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) #define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) - -#define MX35_OTG_BASE_ADDR 0x53ff4000 +#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) +#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) +/* + * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for + * HS. When host support was implemented only a preliminary document was + * available, which told 0x400. This works fine. + */ +#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) #define MX35_ROMP_BASE_ADDR 0x60000000 -#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 #define MX35_ROMP_SIZE SZ_1M #define MX35_AVIC_BASE_ADDR 0x68000000 -#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX35_AVIC_SIZE SZ_1M /* @@ -92,18 +93,17 @@ #define MX35_CS3_BASE_ADDR 0xb2000000 #define MX35_CS4_BASE_ADDR 0xb4000000 -#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX35_CS4_SIZE SZ_32M #define MX35_CS5_BASE_ADDR 0xb6000000 -#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX35_CS5_SIZE SZ_32M /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX35_X_MEMC_BASE_ADDR 0xb8000000 -#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX35_X_MEMC_SIZE SZ_64K #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) @@ -114,12 +114,8 @@ #define MX35_NFC_BASE_ADDR 0xbb000000 #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 -#define MX35_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \ - IMX_IO_ADDRESS(x, MX35_AVIC) ?: \ - IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MX35_SPBA0)) +#define MX35_IO_P2V(x) IMX_IO_P2V(x) +#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) /* * Interrupt numbers @@ -153,8 +149,8 @@ #define MX35_INT_UART2 32 #define MX35_INT_NFC 33 #define MX35_INT_SDMA 34 -#define MX35_INT_USBHS 35 -#define MX35_INT_USBOTG 37 +#define MX35_INT_USB_HS 35 +#define MX35_INT_USB_OTG 37 #define MX35_INT_MSHC1 39 #define MX35_INT_ESAI 40 #define MX35_INT_IPU_ERR 41 @@ -193,20 +189,4 @@ #define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 #define MX35_SYSTEM_REV_NUM 3 -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR -#define MXC_INT_OWIRE MX35_INT_OWIRE -#define MXC_INT_GPU2D MX35_INT_GPU2D -#define MXC_INT_ASRC MX35_INT_ASRC -#define MXC_INT_USBHS MX35_INT_USBHS -#define MXC_INT_USBOTG MX35_INT_USBOTG -#define MXC_INT_ESAI MX35_INT_ESAI -#define MXC_INT_CAN1 MX35_INT_CAN1 -#define MXC_INT_CAN2 MX35_INT_CAN2 -#define MXC_INT_MLB MX35_INT_MLB -#define MXC_INT_SPDIF MX35_INT_SPDIF -#define MXC_INT_FEC MX35_INT_FEC -#endif - #endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index d1bd26d7b8a6..8c7f34e737d0 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -44,7 +44,6 @@ * AIPS 1 */ #define MX3x_AIPS1_BASE_ADDR 0x43f00000 -#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX3x_AIPS1_SIZE SZ_1M #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) @@ -69,7 +68,6 @@ * SPBA global module enabled #0 */ #define MX3x_SPBA0_BASE_ADDR 0x50000000 -#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000 #define MX3x_SPBA0_SIZE SZ_1M #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) @@ -82,7 +80,6 @@ * AIPS 2 */ #define MX3x_AIPS2_BASE_ADDR 0x53f00000 -#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX3x_AIPS2_SIZE SZ_1M #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) @@ -105,11 +102,9 @@ * ROMP and AVIC */ #define MX3x_ROMP_BASE_ADDR 0x60000000 -#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000 #define MX3x_ROMP_SIZE SZ_1M #define MX3x_AVIC_BASE_ADDR 0x68000000 -#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX3x_AVIC_SIZE SZ_1M /* @@ -125,18 +120,17 @@ #define MX3x_CS3_BASE_ADDR 0xb2000000 #define MX3x_CS4_BASE_ADDR 0xb4000000 -#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 #define MX3x_CS4_SIZE SZ_32M #define MX3x_CS5_BASE_ADDR 0xb6000000 -#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 #define MX3x_CS5_SIZE SZ_32M /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 -#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000 #define MX3x_X_MEMC_SIZE SZ_64K #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) @@ -146,56 +140,6 @@ #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 -/*! - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ -#define IO_ADDRESS(x) \ - (void __force __iomem *) \ - (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ - ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ - ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ - ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ - ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ - ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ - ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ - 0xDEADBEEF) - -/* - * define the address mapping macros: in physical address order - */ -#define L2CC_IO_ADDRESS(x) \ - (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) - -#define AIPS1_IO_ADDRESS(x) \ - (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) - -#define SPBA0_IO_ADDRESS(x) \ - (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) - -#define AIPS2_IO_ADDRESS(x) \ - (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) - -#define ROMP_IO_ADDRESS(x) \ - (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) - -#define AVIC_IO_ADDRESS(x) \ - (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) - -#define CS4_IO_ADDRESS(x) \ - (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) - -#define CS5_IO_ADDRESS(x) \ - (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT) - -#define X_MEMC_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - -#define PCMCIA_IO_ADDRESS(x) \ - (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) - /* * Interrupt numbers */ @@ -277,126 +221,4 @@ static inline int mx35_revision(void) } #endif -#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS -/* these should go away */ -#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR -#define L2CC_SIZE MX3x_L2CC_SIZE -#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR -#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT -#define AIPS1_SIZE MX3x_AIPS1_SIZE -#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR -#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR -#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR -#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR -#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR -#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR -#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR -#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR -#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR -#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR -#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR -#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR -#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR -#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR -#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR -#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR -#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR -#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR -#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR -#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT -#define SPBA0_SIZE MX3x_SPBA0_SIZE -#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR -#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR -#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR -#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR -#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR -#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR -#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR -#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT -#define AIPS2_SIZE MX3x_AIPS2_SIZE -#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR -#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR -#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR -#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR -#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR -#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR -#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR -#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR -#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR -#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR -#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR -#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR -#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR -#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR -#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR -#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR -#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR -#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT -#define ROMP_SIZE MX3x_ROMP_SIZE -#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR -#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT -#define AVIC_SIZE MX3x_AVIC_SIZE -#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR -#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR -#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR -#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR -#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR -#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR -#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR -#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR -#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT -#define CS4_SIZE MX3x_CS4_SIZE -#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR -#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT -#define CS5_SIZE MX3x_CS5_SIZE -#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR -#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT -#define X_MEMC_SIZE MX3x_X_MEMC_SIZE -#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR -#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR -#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR -#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR -#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR -#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR -#define MXC_INT_I2C3 MX3x_INT_I2C3 -#define MXC_INT_I2C2 MX3x_INT_I2C2 -#define MXC_INT_RTIC MX3x_INT_RTIC -#define MXC_INT_I2C MX3x_INT_I2C -#define MXC_INT_CSPI2 MX3x_INT_CSPI2 -#define MXC_INT_CSPI1 MX3x_INT_CSPI1 -#define MXC_INT_ATA MX3x_INT_ATA -#define MXC_INT_UART3 MX3x_INT_UART3 -#define MXC_INT_IIM MX3x_INT_IIM -#define MXC_INT_RNGA MX3x_INT_RNGA -#define MXC_INT_EVTMON MX3x_INT_EVTMON -#define MXC_INT_KPP MX3x_INT_KPP -#define MXC_INT_RTC MX3x_INT_RTC -#define MXC_INT_PWM MX3x_INT_PWM -#define MXC_INT_EPIT2 MX3x_INT_EPIT2 -#define MXC_INT_EPIT1 MX3x_INT_EPIT1 -#define MXC_INT_GPT MX3x_INT_GPT -#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL -#define MXC_INT_UART2 MX3x_INT_UART2 -#define MXC_INT_NANDFC MX3x_INT_NANDFC -#define MXC_INT_SDMA MX3x_INT_SDMA -#define MXC_INT_MSHC1 MX3x_INT_MSHC1 -#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR -#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN -#define MXC_INT_UART1 MX3x_INT_UART1 -#define MXC_INT_ECT MX3x_INT_ECT -#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM -#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN -#define MXC_INT_GPIO2 MX3x_INT_GPIO2 -#define MXC_INT_GPIO1 MX3x_INT_GPIO1 -#define MXC_INT_WDOG MX3x_INT_WDOG -#define MXC_INT_GPIO3 MX3x_INT_GPIO3 -#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER -#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER -#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60 -#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61 -#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG -#define MXC_INT_EXT_TV MX3x_INT_EXT_TV -#define PROD_SIGNATURE MX3x_PROD_SIGNATURE -#endif - #endif /* ifndef __MACH_MX3x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 2af7a1056fc1..636347c3fa88 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -2,31 +2,6 @@ #define __MACH_MX51_H__ /* - * MX51 memory map: - * - * - * Virt Phys Size What - * --------------------------------------------------------------------------- - * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM) - * 30000000 256M GPU - * 40000000 512M IPU - * fa200000 60000000 1M DEBUG - * fb100000 70000000 1M SPBA 0 - * fb000000 73f00000 1M AIPS 1 - * fb200000 83f00000 1M AIPS 2 - * 8fffc000 16K TZIC (interrupt controller) - * 90000000 256M CSD0 SDRAM/DDR - * a0000000 256M CSD1 SDRAM/DDR - * b0000000 128M CS0 Flash - * b8000000 128M CS1 Flash - * c0000000 128M CS2 Flash - * c8000000 64M CS3 Flash - * cc000000 32M CS4 SRAM - * ce000000 32M CS5 SRAM - * cfff0000 64K NFC (NAND Flash AXI) - */ - -/* * IROM */ #define MX51_IROM_BASE_ADDR 0x0 @@ -36,7 +11,6 @@ * IRAM */ #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ -#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000 #define MX51_IRAM_PARTITIONS 16 #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ @@ -45,7 +19,6 @@ #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 #define MX51_DEBUG_BASE_ADDR 0x60000000 -#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000 #define MX51_DEBUG_SIZE SZ_1M #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) @@ -61,7 +34,6 @@ * SPBA global module enabled #0 */ #define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 #define MX51_SPBA0_SIZE SZ_1M #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) @@ -81,7 +53,6 @@ * AIPS 1 */ #define MX51_AIPS1_BASE_ADDR 0x73f00000 -#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000 #define MX51_AIPS1_SIZE SZ_1M #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) @@ -109,7 +80,6 @@ * AIPS 2 */ #define MX51_AIPS2_BASE_ADDR 0x83f00000 -#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000 #define MX51_AIPS2_SIZE SZ_1M #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) @@ -163,16 +133,8 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 -#define MX51_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ - IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \ - IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MX51_AIPS2)) - -/* This is currently used in <mach/debug-macro.S>, but should go away */ -#define MX51_AIPS1_IO_ADDRESS(x) \ - (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) +#define MX51_IO_P2V(x) IMX_IO_P2V(x) +#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) /* * defines for SPBA modules diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 0ca3101ebf36..765190fe6332 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -21,14 +21,12 @@ * L2CC */ #define MXC91231_L2CC_BASE_ADDR 0x30000000 -#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000 #define MXC91231_L2CC_SIZE SZ_64K /* * AIPS 1 */ #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 -#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000 #define MXC91231_AIPS1_SIZE SZ_1M #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR @@ -53,7 +51,6 @@ * AIPS 2 */ #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 -#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000 #define MXC91231_AIPS2_SIZE SZ_1M #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) @@ -79,7 +76,6 @@ * SPBA global module 0 */ #define MXC91231_SPBA0_BASE_ADDR 0x50000000 -#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000 #define MXC91231_SPBA0_SIZE SZ_1M #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) @@ -109,7 +105,6 @@ * SPBA global module 1 */ #define MXC91231_SPBA1_BASE_ADDR 0x52000000 -#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000 #define MXC91231_SPBA1_SIZE SZ_1M #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) @@ -144,18 +139,15 @@ * ROMP and AVIC */ #define MXC91231_ROMP_BASE_ADDR 0x60000000 -#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000 #define MXC91231_ROMP_SIZE SZ_64K #define MXC91231_AVIC_BASE_ADDR 0x68000000 -#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000 #define MXC91231_AVIC_SIZE SZ_64K /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 -#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000 #define MXC91231_X_MEMC_SIZE SZ_64K #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) @@ -183,19 +175,10 @@ /* * This macro defines the physical to virtual address mapping for all the * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0. + * and returning the virtual address. */ - -#define MXC91231_IO_ADDRESS(x) ( \ - IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ - IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ - IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ - IMX_IO_ADDRESS(x, MXC91231_AIPS2)) +#define MXC91231_IO_P2V(x) IMX_IO_P2V(x) +#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) /* * Interrupt numbers |