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author | Victor Kamensky <victor.kamensky@linaro.org> | 2014-04-15 20:37:47 +0300 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2014-05-08 07:09:54 -0700 |
commit | 834cacfbef09afc5566eae4dbdc08a422e90451b (patch) | |
tree | 72ec4d38fc42244bd9837442371eeb809cc6aa50 /arch/arm/plat-omap | |
parent | edfaf05c2fcb853fcf35f12aeb9c340f5913337f (diff) | |
download | linux-834cacfbef09afc5566eae4dbdc08a422e90451b.tar.gz linux-834cacfbef09afc5566eae4dbdc08a422e90451b.tar.bz2 linux-834cacfbef09afc5566eae4dbdc08a422e90451b.zip |
ARM: OMAP: dmtimer: raw read and write endian fix
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r-- | arch/arm/plat-omap/dmtimer.c | 8 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/plat/dmtimer.h | 16 |
2 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 869254cebf84..db10169a08de 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -103,7 +103,7 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer) timer->context.tmar); omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr); - __raw_writel(timer->context.tier, timer->irq_ena); + writel_relaxed(timer->context.tier, timer->irq_ena); omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr); } @@ -699,9 +699,9 @@ int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) omap_dm_timer_enable(timer); if (timer->revision == 1) - l = __raw_readl(timer->irq_ena) & ~mask; + l = readl_relaxed(timer->irq_ena) & ~mask; - __raw_writel(l, timer->irq_dis); + writel_relaxed(l, timer->irq_dis); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); @@ -722,7 +722,7 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) return 0; } - l = __raw_readl(timer->irq_stat); + l = readl_relaxed(timer->irq_stat); return l; } diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 2861b155485a..dd79f3005cdf 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -280,20 +280,20 @@ static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, int posted) { if (posted) - while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) + while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); - return __raw_readl(timer->func_base + (reg & 0xff)); + return readl_relaxed(timer->func_base + (reg & 0xff)); } static inline void __omap_dm_timer_write(struct omap_dm_timer *timer, u32 reg, u32 val, int posted) { if (posted) - while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) + while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); - __raw_writel(val, timer->func_base + (reg & 0xff)); + writel_relaxed(val, timer->func_base + (reg & 0xff)); } static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) @@ -301,7 +301,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) u32 tidr; /* Assume v1 ip if bits [31:16] are zero */ - tidr = __raw_readl(timer->io_base); + tidr = readl_relaxed(timer->io_base); if (!(tidr >> 16)) { timer->revision = 1; timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; @@ -385,7 +385,7 @@ static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, } /* Ack possibly pending interrupt */ - __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); + writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); } static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer, @@ -399,7 +399,7 @@ static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer, static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer, unsigned int value) { - __raw_writel(value, timer->irq_ena); + writel_relaxed(value, timer->irq_ena); __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0); } @@ -412,7 +412,7 @@ __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted) static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) { - __raw_writel(value, timer->irq_stat); + writel_relaxed(value, timer->irq_stat); } #endif /* __ASM_ARCH_DMTIMER_H */ |