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| author | Simon Guinot <sguinot@lacie.com> | 2011-07-06 12:41:31 -0400 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2011-07-07 16:02:26 +0000 |
| commit | 659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5 (patch) | |
| tree | a875904f1c457f321563060491956266a57c6514 /arch/arm/plat-samsung | |
| parent | d30e1521b2afb5e6f21ca8bc1a4b6ec2afc93597 (diff) | |
| download | linux-659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5.tar.gz linux-659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5.tar.bz2 linux-659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5.zip | |
genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd)
This fixes a regression introduced by e59347a "arm: orion:
Use generic irq chip".
Depending on the device, interrupts acknowledgement is done by setting
or by clearing a dedicated register. Replace irq_gc_ack() with some
{set,clr}_bit variants allows to handle both cases.
Note that this patch affects the following SoCs: Davinci, Samsung and
Orion. Except for this last, the change is minor: irq_gc_ack() is just
renamed into irq_gc_ack_set_bit().
For the Orion SoCs, the edge GPIO interrupts support is currently
broken. irq_gc_ack() try to acknowledge a such interrupt by setting
the corresponding cause register bit. The Orion GPIO device expect the
opposite. To fix this issue, the irq_gc_ack_clr_bit() variant is used.
Tested on Network Space v2.
Reported-by: Joey Oravec <joravec@drewtech.com>
Signed-off-by: Simon Guinot <sguinot@lacie.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/plat-samsung')
| -rw-r--r-- | arch/arm/plat-samsung/irq-uart.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index 32582c0958e3..0e46588d847b 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c @@ -55,7 +55,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, handle_level_irq); ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack; + ct->chip.irq_ack = irq_gc_ack_set_bit; ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->regs.ack = S3C64XX_UINTP; |