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author | Sudeep Holla <sudeep.holla@arm.com> | 2016-06-02 10:18:41 +0100 |
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committer | Sudeep Holla <sudeep.holla@arm.com> | 2016-06-21 15:10:56 +0100 |
commit | 3e287cf6ef954947365a4aca6580ea1d6bee3a18 (patch) | |
tree | 12eb9ee5888d6ce65246666649ec54fc5b3b49aa /arch/arm64/boot/dts/arm/juno.dts | |
parent | 1a695a905c18548062509178b98bc91e67510864 (diff) | |
download | linux-3e287cf6ef954947365a4aca6580ea1d6bee3a18.tar.gz linux-3e287cf6ef954947365a4aca6580ea1d6bee3a18.tar.bz2 linux-3e287cf6ef954947365a4aca6580ea1d6bee3a18.zip |
arm64: dts: juno: add coresight support
Most of the debug-related components on Juno are located in the coreSight
subsystem while others are located in the Cortex-Axx clusters, the SCP
subsystem, and in the main system.
Each core in the two processor clusters contain an Embedded Trace
Macrocell(ETM) which generates real-time trace information that trace
tools can use and an ATB trace output that is sent to a funnel before
going to the CoreSight subsystem.
The trace output signals combine with two trace expansions using another
funnel and fed into the Embedded Trace FIFO(ETF0).
The output trace data stream of the funnel is then replicated before it
is sent to either the:
- Trace Port Interface Unit(TPIU), that sends it out using the trace port.
- ETR that can write the trace data to memory located in the application
memory space
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'arch/arm64/boot/dts/arm/juno.dts')
-rw-r--r-- | arch/arm64/boot/dts/arm/juno.dts | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index dcfcf15a17f5..a7270eff6939 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -173,3 +173,27 @@ #include "juno-base.dtsi" }; + +&etm0 { + cpu = <&A57_0>; +}; + +&etm1 { + cpu = <&A57_1>; +}; + +&etm2 { + cpu = <&A53_0>; +}; + +&etm3 { + cpu = <&A53_1>; +}; + +&etm4 { + cpu = <&A53_2>; +}; + +&etm5 { + cpu = <&A53_3>; +}; |