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| author | Rob Rice <rrice@broadcom.com> | 2016-05-24 14:07:30 -0400 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2016-11-07 09:03:31 -0800 |
| commit | e79249143f468f8d3365dbbd1642c045bdcc98c5 (patch) | |
| tree | 8f2d60a3eebf3d1a0b43da4555b10dfaadacb209 /arch/arm64/boot/dts/broadcom/ns2.dtsi | |
| parent | 62b69232d68114387b2e4bd30d258e4279b85de4 (diff) | |
| download | linux-e79249143f468f8d3365dbbd1642c045bdcc98c5.tar.gz linux-e79249143f468f8d3365dbbd1642c045bdcc98c5.tar.bz2 linux-e79249143f468f8d3365dbbd1642c045bdcc98c5.zip | |
arm64: dts: Add Broadcom Northstar2 device tree entries for PDC driver.
Add Broadcom Northstar2 SoC device tree entries for PDC driver.
Signed-off-by: Rob Rice <rob.rice@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/broadcom/ns2.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/broadcom/ns2.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index f05b28b4856f..cb09981c132c 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -191,6 +191,42 @@ #include "ns2-clock.dtsi" + pdc0: iproc-pdc0@612c0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612c0000 0x445>; /* PDC FS0 regs */ + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + pdc1: iproc-pdc1@612e0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612e0000 0x445>; /* PDC FS1 regs */ + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + pdc2: iproc-pdc2@61300000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x61300000 0x445>; /* PDC FS2 regs */ + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + pdc3: iproc-pdc3@61320000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x61320000 0x445>; /* PDC FS3 regs */ + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + dma0: dma@61360000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x61360000 0x1000>; |