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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2019-10-04 16:27:24 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-09 09:36:40 +0200 |
| commit | cbafcad0641e99831ff7c57ac8f79aed502f33e5 (patch) | |
| tree | 21cebba0c69931d3f48127235a948956084a47d4 /arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | |
| parent | 6a380172f171d81259e90ddc99d25fec20e56e1e (diff) | |
| download | linux-cbafcad0641e99831ff7c57ac8f79aed502f33e5.tar.gz linux-cbafcad0641e99831ff7c57ac8f79aed502f33e5.tar.bz2 linux-cbafcad0641e99831ff7c57ac8f79aed502f33e5.zip | |
arm64: dts: marvell: Add support for AP807/AP807-quad
Describe AP807 and AP807-quad support.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi new file mode 100644 index 000000000000..65364691257d --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for Marvell Armada AP807 Quad + * + * Copyright (C) 2019 Marvell Technology Group Ltd. + */ + +#include "armada-ap807.dtsi" + +/ { + model = "Marvell Armada AP807 Quad"; + compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x000>; + enable-method = "psci"; + #cooling-cells = <2>; + clocks = <&cpu_clk 0>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x001>; + enable-method = "psci"; + #cooling-cells = <2>; + clocks = <&cpu_clk 0>; + }; + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + clocks = <&cpu_clk 1>; + }; + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + #cooling-cells = <2>; + clocks = <&cpu_clk 1>; + }; + }; +}; |