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| author | Andy Lutomirski <luto@amacapital.net> | 2014-10-15 10:12:07 -0700 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2014-10-22 21:31:46 +0200 |
| commit | b47dcbdc5161d3d5756f430191e2840d9b855492 (patch) | |
| tree | ea77258bd506a4f59ac0575828d016dfdba2414e /arch/arm64/include/asm/hw_breakpoint.h | |
| parent | 961b6a7003acec4f9d70dabc1a253b783cb74272 (diff) | |
| download | linux-b47dcbdc5161d3d5756f430191e2840d9b855492.tar.gz linux-b47dcbdc5161d3d5756f430191e2840d9b855492.tar.bz2 linux-b47dcbdc5161d3d5756f430191e2840d9b855492.zip | |
x86, apic: Handle a bad TSC more gracefully
If the TSC is unusable or disabled, then this patch fixes:
- Confusion while trying to clear old APIC interrupts.
- Division by zero and incorrect programming of the TSC deadline
timer.
This fixes boot if the CPU has a TSC deadline timer but a missing or
broken TSC. The failure to boot can be observed with qemu using
-cpu qemu64,-tsc,+tsc-deadline
This also happens to me in nested KVM for unknown reasons.
With this patch, I can boot cleanly (although without a TSC).
Signed-off-by: Andy Lutomirski <luto@amacapital.net>
Cc: Bandan Das <bsd@redhat.com>
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/e2fa274e498c33988efac0ba8b7e3120f7f92d78.1413393027.git.luto@amacapital.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm64/include/asm/hw_breakpoint.h')
0 files changed, 0 insertions, 0 deletions