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| author | Will Deacon <will.deacon@arm.com> | 2018-06-15 11:37:34 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-09-14 17:46:01 +0100 |
| commit | d71be2b6c0e19180b5f80a6d42039cc074a693a2 (patch) | |
| tree | a76f555a9b74a6a8e8ed9733e7eac60c6f880ec6 /arch/arm64/include/uapi | |
| parent | ca7f686ac9fe87a9175696a8744e095ab9749c49 (diff) | |
| download | linux-d71be2b6c0e19180b5f80a6d42039cc074a693a2.tar.gz linux-d71be2b6c0e19180b5f80a6d42039cc074a693a2.tar.bz2 linux-d71be2b6c0e19180b5f80a6d42039cc074a693a2.zip | |
arm64: cpufeature: Detect SSBS and advertise to userspace
Armv8.5 introduces a new PSTATE bit known as Speculative Store Bypass
Safe (SSBS) which can be used as a mitigation against Spectre variant 4.
Additionally, a CPU may provide instructions to manipulate PSTATE.SSBS
directly, so that userspace can toggle the SSBS control without trapping
to the kernel.
This patch probes for the existence of SSBS and advertise the new instructions
to userspace if they exist.
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/uapi')
| -rw-r--r-- | arch/arm64/include/uapi/asm/hwcap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 17c65c8f33cb..2bcd6e4f3474 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -48,5 +48,6 @@ #define HWCAP_USCAT (1 << 25) #define HWCAP_ILRCPC (1 << 26) #define HWCAP_FLAGM (1 << 27) +#define HWCAP_SSBS (1 << 28) #endif /* _UAPI__ASM_HWCAP_H */ |