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| author | Arnd Bergmann <arnd@arndb.de> | 2017-08-04 12:53:21 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2017-08-04 12:53:21 +0200 |
| commit | 48cb953e6d899f2b0fb38c8b69c260929107ad4c (patch) | |
| tree | d4630e459a414001970d95f289be46da6afa9afa /arch/arm64 | |
| parent | b99bba09a57591f4fe6d3704fb386ca3ae588c9c (diff) | |
| parent | d7a65c4905bc9c304ecf3d8aa566802f6119480f (diff) | |
| download | linux-48cb953e6d899f2b0fb38c8b69c260929107ad4c.tar.gz linux-48cb953e6d899f2b0fb38c8b69c260929107ad4c.tar.bz2 linux-48cb953e6d899f2b0fb38c8b69c260929107ad4c.zip | |
Merge tag 'mvebu-fixes-4.13-2' of git://git.infradead.org/linux-mvebu into fixes
Pull "mvebu fixes for 4.13 (part 2)" from Gregory CLEMENT:
All the fixes are for ARM64 mvebu:
- Fix the RTC interrupt on A7K/A8K which was missed when switching
from GIC to ICU
- Mark the A7K/A8K crypto engine as dma coherent
- Fix the number of GPIO on south bridge on Armada 3700
* tag 'mvebu-fixes-4.13-2' of git://git.infradead.org/linux-mvebu:
ARM64: dts: marvell: armada-37xx: Fix the number of GPIO on south bridge
arm64: dts: marvell: mark the cp110 crypto engine as dma coherent
arm64: dts: marvell: use ICU for the CP110 slave RTC
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 3 |
3 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index dbcc3d4e2ed5..51763d674050 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -219,7 +219,7 @@ reg = <0x18800 0x100>, <0x18C00 0x20>; gpiosb: gpio { #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-ranges = <&pinctrl_sb 0 0 30>; gpio-controller; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 726528ce54e9..4c68605675a8 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -270,6 +270,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cpm_clk 1 26>; + dma-coherent; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 95f8e5f607f6..923f354b02f0 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -64,7 +64,7 @@ compatible = "marvell,armada-8k-rtc"; reg = <0x284000 0x20>, <0x284080 0x24>; reg-names = "rtc", "rtc-soc"; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>; }; cps_ethernet: ethernet@0 { @@ -261,6 +261,7 @@ interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cps_clk 1 26>; + dma-coherent; /* * The cryptographic engine found on the cp110 * master is enabled by default at the SoC |