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| author | Olof Johansson <olof@lixom.net> | 2017-01-29 21:15:52 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2017-01-29 21:15:52 -0800 |
| commit | 84b4e9f5a83e9d0afd3aed4c2272815719af6f84 (patch) | |
| tree | 7d6297d323963b88a89d343510997eefe4a9e189 /arch/arm64 | |
| parent | ac43d9e0e5647052d78ba1e8d939549262fc268e (diff) | |
| parent | eb2e2a816834cab13311d627844d77bb22bb5787 (diff) | |
| download | linux-84b4e9f5a83e9d0afd3aed4c2272815719af6f84.tar.gz linux-84b4e9f5a83e9d0afd3aed4c2272815719af6f84.tar.bz2 linux-84b4e9f5a83e9d0afd3aed4c2272815719af6f84.zip | |
Merge tag 'zte-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
ZTE arm64 device tree update for 4.11:
- Enable cpufreq support for zx296718 by using new operating-points-v2
bindings, so that it works with the generic cpufreq-dt driver.
* tag 'zte-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: zx: support cpu-freq for zx296718
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/zte/zx296718.dtsi | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi index 88ff70a06086..b850b2cd0adc 100644 --- a/arch/arm64/boot/dts/zte/zx296718.dtsi +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi @@ -44,6 +44,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/zx296718-clock.h> / { compatible = "zte,zx296718"; @@ -81,6 +82,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -88,6 +91,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -95,6 +100,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -102,6 +109,38 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; + }; + }; + + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <500000>; + }; + + opp@648000000 { + opp-hz = /bits/ 64 <648000000>; + clock-latency-ns = <500000>; + }; + + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + clock-latency-ns = <500000>; + }; + + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <500000>; + }; + + opp@1188000000 { + opp-hz = /bits/ 64 <1188000000>; + clock-latency-ns = <500000>; }; }; |