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| author | Will Deacon <will.deacon@arm.com> | 2018-12-13 13:47:38 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-13 14:14:21 +0000 |
| commit | 2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1 (patch) | |
| tree | eb156e26883d666f26909dfa50d3d206848f885f /arch/arm64 | |
| parent | b47f515bdcd4e22b0b87141157c9ee8bc7c9bb98 (diff) | |
| download | linux-2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1.tar.gz linux-2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1.tar.bz2 linux-2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1.zip | |
arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field
While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
to see if a CPU is susceptible to Meltdown and therefore requires kpti
to be enabled, existing CPUs do not implement this field.
We therefore whitelist all unaffected Cortex-A CPUs that do not implement
the CSV3 field.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e6467e64ee91..7b6f26fd075f 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -946,6 +946,12 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, static const struct midr_range kpti_safe_list[] = { MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), { /* sentinel */ } }; char const *str = "command line option"; |