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authorNishanth Menon <nm@ti.com>2014-02-13 23:45:49 -0600
committerChris Ball <chris@printf.net>2014-03-04 11:44:35 -0500
commita8d6fb5de83bc49f8feccdc34a8663978f74820c (patch)
tree564550efd7e85e42d7c6df3cc182f1f5644a43b1 /arch/arm
parent59445b10d08144d870d8340ce25634014bf972d5 (diff)
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ARM: dts: omap3-ldp: fix mmc configuration
MMC1 is the only MMC interface available on the platform. Further, since the platform is based on older revision of SoC which is not capable of doing multi-block reads, mark it with compatibility for the same and add pinmux to ensure that all relevant pins are configured for non-MMC boot mode. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Balaji T K <balajitk@ti.com> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/omap3-ldp.dts23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index ddce0d807f70..0abe986a4ecc 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -174,8 +174,20 @@
};
&mmc1 {
+ /* See 35xx errata 2.1.1.128 in SPRZ278F */
+ compatible = "ti,omap3-pre-es3-hsmmc";
vmmc-supply = <&vmmc1>;
bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+};
+
+&mmc2 {
+ status="disabled";
+};
+
+&mmc3 {
+ status="disabled";
};
&omap3_pmx_core {
@@ -209,6 +221,17 @@
0x174 (PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
>;
};
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
+ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
+ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
+ OMAP3_CORE1_IOPAD(0x214A, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
+ OMAP3_CORE1_IOPAD(0x214C, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
+ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
+ >;
+ };
};
&usb_otg_hs {