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authorWolfram Sang <w.sang@pengutronix.de>2011-09-10 12:29:43 +0200
committerShawn Guo <shawn.guo@linaro.org>2012-01-27 11:50:14 +0800
commita62407256bbcba8e3f62695a87534050ceec0e6f (patch)
treeecd2c62f50c6a3f752ff7cfb9f5bae3a382e9e2a /arch/arm
parentbfc0b9c8a9d546eb53a3491c893fad72d96540cb (diff)
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ARM: mx28: check for gated clocks when setting saif divider
Like with all other clocks, the divider for the SAIF devices should not be altered when the clock is gated. Bail out when this is the case like the other clocks do. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Dong Aisheng-B29396 <B29396@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index f71d01282dcd..54d82a4b4cf0 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -477,6 +477,10 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
reg &= ~BM_CLKCTRL_##rs##_DIV; \
reg |= div << BP_CLKCTRL_##rs##_DIV; \
+ if (reg & (1 << clk->enable_shift)) { \
+ pr_err("%s: clock is gated\n", __func__); \
+ return -EINVAL; \
+ } \
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
\
for (i = 10000; i; i--) \