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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-01-05 11:30:37 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-01-05 11:30:37 -0800 |
commit | b23b0ea3708c3dec599966fc856836aca48835b9 (patch) | |
tree | d911a2ae33b7f546e8408e7a2aef845f65a3d881 /arch/arm | |
parent | 078a5a4faf64fefaf13478a9091782432cad33fa (diff) | |
parent | 00f8ccd0c95f4e604297057a5bccec86c0903d14 (diff) | |
download | linux-b23b0ea3708c3dec599966fc856836aca48835b9.tar.gz linux-b23b0ea3708c3dec599966fc856836aca48835b9.tar.bz2 linux-b23b0ea3708c3dec599966fc856836aca48835b9.zip |
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull more ARM SoC updates from Olof Johansson:
"A few updates that we merged late but are low risk for regressions for
other platforms (and a few other straggling patches):
- I mis-tagged the 'drivers' branch, and missed 3 patches. Merged in
here. They're for a driver for the PL353 SRAM controller and a
build fix for the qualcomm scm driver.
- A new platform, RDA Micro RDA8810PL (Cortex-A5 w/ integrated
Vivante GPU, 256MB RAM, Wifi). This includes some acked
platform-specific drivers (serial, etc). This also include DTs for
two boards with this SoC, OrangePi 2G and OrangePi i86.
- i.MX8 is another new platform (NXP, 4x Cortex-A53 + Cortex-M4, 4K
video playback offload). This is the first i.MX 64-bit SoC.
- Some minor updates to Samsung boards (adding a few peripherals in
DTs).
- Small rework for SMP bootup on STi platforms.
- A couple of TEE driver fixes.
- A couple of new config options (bcm2835 thermal, Uniphier MDMAC)
enabled in defconfigs"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits)
ARM: multi_v7_defconfig: enable CONFIG_UNIPHIER_MDMAC
arm64: defconfig: Re-enable bcm2835-thermal driver
MAINTAINERS: Add entry for RDA Micro SoC architecture
tty: serial: Add RDA8810PL UART driver
ARM: dts: rda8810pl: Add interrupt support for UART
dt-bindings: serial: Document RDA Micro UART
ARM: dts: rda8810pl: Add timer support
ARM: dts: Add devicetree for OrangePi i96 board
ARM: dts: Add devicetree for OrangePi 2G IoT board
ARM: dts: Add devicetree for RDA8810PL SoC
ARM: Prepare RDA8810PL SoC
dt-bindings: arm: Document RDA8810PL and reference boards
dt-bindings: Add RDA Micro vendor prefix
ARM: sti: remove pen_release and boot_lock
arm64: dts: exynos: Add Bluetooth chip to TM2(e) boards
arm64: dts: imx8mq-evk: enable watchdog
arm64: dts: imx8mq: add watchdog devices
MAINTAINERS: add i.MX8 DT path to i.MX architecture
arm64: add support for i.MX8M EVK board
arm64: add basic DTS for i.MX8MQ
...
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/Kconfig | 2 | ||||
-rw-r--r-- | arch/arm/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/boot/dts/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts | 50 | ||||
-rw-r--r-- | arch/arm/boot/dts/rda8810pl-orangepi-i96.dts | 50 | ||||
-rw-r--r-- | arch/arm/boot/dts/rda8810pl.dtsi | 99 | ||||
-rw-r--r-- | arch/arm/configs/multi_v7_defconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-rda/Kconfig | 7 | ||||
-rw-r--r-- | arch/arm/mach-rda/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/mach-sti/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-sti/headsmp.S | 43 | ||||
-rw-r--r-- | arch/arm/mach-sti/platsmp.c | 88 |
12 files changed, 229 insertions, 118 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c1227757817b..664e918e2624 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -787,6 +787,8 @@ source "arch/arm/plat-pxa/Kconfig" source "arch/arm/mach-qcom/Kconfig" +source "arch/arm/mach-rda/Kconfig" + source "arch/arm/mach-realview/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 0436002d5091..9db3c584b2cb 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -202,6 +202,7 @@ machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_QCOM) += qcom +machine-$(CONFIG_ARCH_RDA) += rda machine-$(CONFIG_ARCH_REALVIEW) += realview machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 78551c4375d5..bd40148a15b2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -822,6 +822,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8974-sony-xperia-castor.dtb \ qcom-msm8974-sony-xperia-honami.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb +dtb-$(CONFIG_ARCH_RDA) += \ + rda8810pl-orangepi-2g-iot.dtb \ + rda8810pl-orangepi-i96.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ arm-realview-pb11mp.dtb \ diff --git a/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts b/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts new file mode 100644 index 000000000000..98e34248ae80 --- /dev/null +++ b/arch/arm/boot/dts/rda8810pl-orangepi-2g-iot.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "rda8810pl.dtsi" + +/ { + compatible = "xunlong,orangepi-2g-iot", "rda,8810pl"; + model = "Orange Pi 2G-IoT"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + chosen { + stdout-path = "serial2:921600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&uart1 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart2 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart3 { + status = "okay"; + clocks = <&uart_clk>; +}; diff --git a/arch/arm/boot/dts/rda8810pl-orangepi-i96.dts b/arch/arm/boot/dts/rda8810pl-orangepi-i96.dts new file mode 100644 index 000000000000..728f76931b99 --- /dev/null +++ b/arch/arm/boot/dts/rda8810pl-orangepi-i96.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "rda8810pl.dtsi" + +/ { + compatible = "xunlong,orangepi-i96", "rda,8810pl"; + model = "Orange Pi i96"; + + aliases { + serial0 = &uart2; + serial1 = &uart1; + serial2 = &uart3; + }; + + chosen { + stdout-path = "serial2:921600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&uart1 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart2 { + status = "okay"; + clocks = <&uart_clk>; +}; + +&uart3 { + status = "okay"; + clocks = <&uart_clk>; +}; diff --git a/arch/arm/boot/dts/rda8810pl.dtsi b/arch/arm/boot/dts/rda8810pl.dtsi new file mode 100644 index 000000000000..19cde895bf65 --- /dev/null +++ b/arch/arm/boot/dts/rda8810pl.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RDA8810PL SoC + * + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "rda,8810pl"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0x0>; + }; + }; + + sram@100000 { + compatible = "mmio-sram"; + reg = <0x100000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + apb@20800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20800000 0x100000>; + + intc: interrupt-controller@0 { + compatible = "rda,8810pl-intc"; + reg = <0x0 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + apb@20900000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20900000 0x100000>; + + timer@10000 { + compatible = "rda,8810pl-timer"; + reg = <0x10000 0x1000>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>, + <17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hwtimer", "ostimer"; + }; + }; + + apb@20a00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20a00000 0x100000>; + + uart1: serial@0 { + compatible = "rda,8810pl-uart"; + reg = <0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart2: serial@10000 { + compatible = "rda,8810pl-uart"; + reg = <0x10000 0x1000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart3: serial@90000 { + compatible = "rda,8810pl-uart"; + reg = <0x90000 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + l2: cache-controller@21100000 { + compatible = "arm,pl310-cache"; + reg = <0x21100000 0x1000>; + cache-unified; + cache-level = <2>; + }; +}; diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index f29f49a9f36c..5bee34a7ff2e 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -867,6 +867,7 @@ CONFIG_STM32_DMA=y CONFIG_STM32_DMAMUX=y CONFIG_STM32_MDMA=y CONFIG_TEGRA20_APB_DMA=y +CONFIG_UNIPHIER_MDMAC=y CONFIG_XILINX_DMA=y CONFIG_QCOM_BAM_DMA=y CONFIG_DW_DMAC=y diff --git a/arch/arm/mach-rda/Kconfig b/arch/arm/mach-rda/Kconfig new file mode 100644 index 000000000000..4df8b8ee1a9d --- /dev/null +++ b/arch/arm/mach-rda/Kconfig @@ -0,0 +1,7 @@ +menuconfig ARCH_RDA + bool "RDA Micro SoCs" + depends on ARCH_MULTI_V7 + select RDA_INTC + select RDA_TIMER + help + This enables support for the RDA Micro 8810PL SoC family. diff --git a/arch/arm/mach-rda/Makefile b/arch/arm/mach-rda/Makefile new file mode 100644 index 000000000000..6bea3d3a2dd7 --- /dev/null +++ b/arch/arm/mach-rda/Makefile @@ -0,0 +1 @@ +obj- += dummy.o diff --git a/arch/arm/mach-sti/Makefile b/arch/arm/mach-sti/Makefile index acb330916333..f85ff059cfba 100644 --- a/arch/arm/mach-sti/Makefile +++ b/arch/arm/mach-sti/Makefile @@ -1,2 +1,2 @@ -obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_ARCH_STI) += board-dt.o diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S deleted file mode 100644 index e0ad451700d5..000000000000 --- a/arch/arm/mach-sti/headsmp.S +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/arm/mach-sti/headsmp.S - * - * Copyright (C) 2013 STMicroelectronics (R&D) Limited. - * http://www.st.com - * - * Cloned from linux/arch/arm/mach-vexpress/headsmp.S - * - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <linux/init.h> - -/* - * ST specific entry point for secondary CPUs. This provides - * a "holding pen" into which all secondary cores are held until we're - * ready for them to initialise. - */ -ENTRY(sti_secondary_startup) - mrc p15, 0, r0, c0, c0, 5 - and r0, r0, #15 - adr r4, 1f - ldmia r4, {r5, r6} - sub r4, r4, r5 - add r6, r6, r4 -pen: ldr r7, [r6] - cmp r7, r0 - bne pen - - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup -ENDPROC(sti_secondary_startup) - -1: .long . - .long pen_release diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c index 231f19e17436..d0272a839ffb 100644 --- a/arch/arm/mach-sti/platsmp.c +++ b/arch/arm/mach-sti/platsmp.c @@ -28,82 +28,33 @@ #include "smp.h" -static void write_pen_release(int val) -{ - pen_release = val; - smp_wmb(); - sync_cache_w(&pen_release); -} - -static DEFINE_SPINLOCK(boot_lock); - -static void sti_secondary_init(unsigned int cpu) -{ - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} +static u32 __iomem *cpu_strt_ptr; static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) { - unsigned long timeout; - - /* - * set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); + unsigned long entry_pa = __pa_symbol(secondary_startup); /* - * The secondary processor is waiting to be released from - * the holding pen - release it, then wait for it to flag - * that it has been released by resetting pen_release. - * - * Note that "pen_release" is the hardware CPU ID, whereas - * "cpu" is Linux's internal ID. + * Secondary CPU is initialised and started by a U-BOOTROM firmware. + * Secondary CPU is spinning and waiting for a write at cpu_strt_ptr. + * Writing secondary_startup address at cpu_strt_ptr makes it to + * jump directly to secondary_startup(). */ - write_pen_release(cpu_logical_map(cpu)); + __raw_writel(entry_pa, cpu_strt_ptr); - /* - * Send the secondary CPU a soft interrupt, thereby causing - * it to jump to the secondary entrypoint. - */ - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); - - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (pen_release == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); + /* wmb so that data is actually written before cache flush is done */ + smp_wmb(); + sync_cache_w(cpu_strt_ptr); - return pen_release != -1 ? -ENOSYS : 0; + return 0; } static void __init sti_smp_prepare_cpus(unsigned int max_cpus) { struct device_node *np; void __iomem *scu_base; - u32 __iomem *cpu_strt_ptr; u32 release_phys; int cpu; - unsigned long entry_pa = __pa_symbol(sti_secondary_startup); np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); @@ -131,8 +82,8 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus) } /* - * holding pen is usually configured in SBC DMEM but can also be - * in RAM. + * cpu-release-addr is usually configured in SBC DMEM but can + * also be in RAM. */ if (!memblock_is_memory(release_phys)) @@ -142,22 +93,11 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus) cpu_strt_ptr = (u32 __iomem *)phys_to_virt(release_phys); - __raw_writel(entry_pa, cpu_strt_ptr); - - /* - * wmb so that data is actually written - * before cache flush is done - */ - smp_wmb(); - sync_cache_w(cpu_strt_ptr); - - if (!memblock_is_memory(release_phys)) - iounmap(cpu_strt_ptr); + set_cpu_possible(cpu, true); } } const struct smp_operations sti_smp_ops __initconst = { .smp_prepare_cpus = sti_smp_prepare_cpus, - .smp_secondary_init = sti_secondary_init, .smp_boot_secondary = sti_boot_secondary, }; |