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authorDongjin Kim <tobetter@gmail.com>2013-02-04 21:30:15 -0800
committerKukjin Kim <kgene.kim@samsung.com>2013-03-07 19:39:50 +0900
commitec34d52e2adb48d961dc51037886f2373a3407d2 (patch)
tree37c184e397ecb92dce69429182e44fe627cb3a5e /arch/arm
parente88d5ae61a00b602cdd6a6c07f9fe6fbcaad06d7 (diff)
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ARM: dts: Fix the timing property of MSHC controller for exynos4412-odroidx
This fixes the property of dw-mshc-sdr-timing and dw-mshc-ddr-timing as per its current binding, it only has two cells. Signed-off-by: Dongjin Kim <tobetter@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx.dts4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index f41a84e00f5d..009a9c2a0df7 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -49,8 +49,8 @@
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3 3>;
- samsung,dw-mshc-ddr-timing = <1 2 3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;