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| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-08-15 17:40:05 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2012-09-07 20:02:05 +0300 |
| commit | 4dc3eed450ea74b33e1c0552b5889ed225c33c9a (patch) | |
| tree | 52b310766bb7e0a3fdd1746bdbd3d762120fad08 /arch/arm | |
| parent | ee144e645a081daad5de1ccac77f0a0e98e6a67b (diff) | |
| download | linux-4dc3eed450ea74b33e1c0552b5889ed225c33c9a.tar.gz linux-4dc3eed450ea74b33e1c0552b5889ed225c33c9a.tar.bz2 linux-4dc3eed450ea74b33e1c0552b5889ed225c33c9a.zip | |
OMAP: 4430SDP: remove DSI clock config from board file
DSI clocks are now configured dynamically by the DSI driver, so we can
remove the hardcoded clock configuration from the board file.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-omap2/board-4430sdp.c | 46 |
1 files changed, 0 insertions, 46 deletions
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 2c151c28cca1..c165e20506c9 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -621,29 +621,6 @@ static struct omap_dss_device sdp4430_lcd_device = { .phy.dsi = { .module = 0, }, - - .clocks = { - .dispc = { - .channel = { - /* Logic Clock = 172.8 MHz */ - .lck_div = 1, - /* Pixel Clock = 34.56 MHz */ - .pck_div = 5, - .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, - }, - .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK, - }, - - .dsi = { - .regn = 16, /* Fint = 2.4 MHz */ - .regm = 180, /* DDR Clock = 216 MHz */ - .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */ - .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */ - - .lp_clk_div = 10, /* LP Clock = 8.64 MHz */ - .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, - }, - }, .channel = OMAP_DSS_CHANNEL_LCD, }; @@ -668,29 +645,6 @@ static struct omap_dss_device sdp4430_lcd2_device = { .module = 1, }, - - .clocks = { - .dispc = { - .channel = { - /* Logic Clock = 172.8 MHz */ - .lck_div = 1, - /* Pixel Clock = 34.56 MHz */ - .pck_div = 5, - .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, - }, - .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK, - }, - - .dsi = { - .regn = 16, /* Fint = 2.4 MHz */ - .regm = 180, /* DDR Clock = 216 MHz */ - .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */ - .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */ - - .lp_clk_div = 10, /* LP Clock = 8.64 MHz */ - .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, - }, - }, .channel = OMAP_DSS_CHANNEL_LCD2, }; |