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authorMike Frysinger <vapier@gentoo.org>2011-04-15 13:04:59 -0400
committerMike Frysinger <vapier@gentoo.org>2011-05-25 08:13:43 -0400
commit8c0541035007bd8bbacfc5d71c696cdf37696794 (patch)
tree3731d537dcb31b6decfc5493be6f4d5f3d055fb2 /arch/blackfin/mach-bf537/include/mach
parente2a8092c3fa9766248e9515252ae44e6df2d97a0 (diff)
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Blackfin: bf537: demux port H mask A and emac rx ints
The BF537 SIC combines the gpio port H mask A interrupts with the emac rx interrupt, so we need to demux this in software. It also combines the gpio port H mask B and the emac tx interrupts, and the watchdog and port F mask B interrupts, but since we don't support mask B yet, just add the defines for now. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf537/include/mach')
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h33
1 files changed, 26 insertions, 7 deletions
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index cc3132347414..b6ed8235bda4 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -28,8 +28,8 @@
#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
-#define IRQ_MAC_RX BFIN_IRQ(17) /* DMA1 (Ethernet RX) Interrupt */
-#define IRQ_MAC_TX BFIN_IRQ(18) /* DMA2 (Ethernet TX) Interrupt */
+#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
@@ -38,12 +38,11 @@
#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
-#define IRQ_PROG_INTA BFIN_IRQ(27) /* PF Ports F&G (PF15:0) Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(28) /* PF Port G (PF15:0) Interrupt B */
+#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
+#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
-#define IRQ_PROG_INTB BFIN_IRQ(31) /* PF Ports F (PF15:0) Interrupt B */
-#define IRQ_WATCH BFIN_IRQ(32) /* Watch Dog Timer */
+#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
#define SYS_IRQS 39
@@ -118,7 +117,27 @@
#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
+#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
+
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
+#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
+#else
+#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
+#endif
+
+#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
+#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
+
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_WATCH 112 /* Watchdog Timer */
+#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
+#else
+#define IRQ_WATCH IRQ_PF_INTB_WATCH
+#endif
+
+#define NR_MACH_IRQS (113 + 1)
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0