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| author | Mike Frysinger <vapier@gentoo.org> | 2010-10-19 17:57:54 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-10-22 16:30:01 -0400 |
| commit | 9ebcaa47ba831b6ad5cc414b3c3ff310a9d5d582 (patch) | |
| tree | d5d63490da2e9f031e547234f2d4e2031a2397ef /arch/blackfin/mach-bf548 | |
| parent | 49e00edbb77b44574a235032774b15656faa7cec (diff) | |
| download | linux-9ebcaa47ba831b6ad5cc414b3c3ff310a9d5d582.tar.gz linux-9ebcaa47ba831b6ad5cc414b3c3ff310a9d5d582.tar.bz2 linux-9ebcaa47ba831b6ad5cc414b3c3ff310a9d5d582.zip | |
Blackfin: bf54x: add missing SIC_RVECT definition
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h | 2 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/defBF54x_base.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h index 0c16067df4f3..deaf5d6542d5 100644 --- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h @@ -40,6 +40,8 @@ /* SIC Registers */ +#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index 35707b17020e..78f91103f175 100644 --- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h @@ -35,6 +35,7 @@ /* SIC Registers */ +#define SIC_RVECT 0xffc00108 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ |