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| author | Mike Frysinger <vapier@gentoo.org> | 2009-06-29 14:20:10 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-07-16 01:52:24 -0400 |
| commit | fb4b5d3a379824d94fd71fc1aa78e9dbcb15b948 (patch) | |
| tree | 104b640b09ebbc58f4eb3b67fd190bf7bf9a3912 /arch/blackfin/mach-bf561/include | |
| parent | 8399a74f61c69c7d233924de3dd314ca0effa16a (diff) | |
| download | linux-fb4b5d3a379824d94fd71fc1aa78e9dbcb15b948.tar.gz linux-fb4b5d3a379824d94fd71fc1aa78e9dbcb15b948.tar.bz2 linux-fb4b5d3a379824d94fd71fc1aa78e9dbcb15b948.zip | |
Blackfin: handle BF561 Core B memory regions better when SMP=n
Rather than assume Core B is always run with caches turned on, let people
load into any of the on-chip memory regions. It is their business how the
SRAM/Cache regions are utilized, so don't prevent them from being able to
load into them.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/include')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/mem_map.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h index a63e15c86d90..5b96ea549a04 100644 --- a/arch/blackfin/mach-bf561/include/mach/mem_map.h +++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h @@ -37,7 +37,6 @@ /* Memory Map for ADSP-BF561 processors */ -#ifdef CONFIG_BF561 #define COREA_L1_CODE_START 0xFFA00000 #define COREA_L1_DATA_A_START 0xFF800000 #define COREA_L1_DATA_B_START 0xFF900000 @@ -74,6 +73,28 @@ #define BFIN_DCACHESIZE (0*1024) #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE*/ + +/* + * If we are in SMP mode, then the cache settings of Core B will match + * the settings of Core A. If we aren't, then we assume Core B is not + * using any cache. This allows the rest of the kernel to work with + * the core in either mode as we are only loading user code into it and + * it is the user's problem to make sure they aren't doing something + * stupid there. + * + * Note that we treat the L1 code region as a contiguous blob to make + * the rest of the kernel simpler. Easier to check one region than a + * bunch of small ones. Again, possible misbehavior here is the fault + * of the user -- don't try to use memory that doesn't exist. + */ +#ifdef CONFIG_SMP +# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH +# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH +# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH +#else +# define COREB_L1_CODE_LENGTH 0x14000 +# define COREB_L1_DATA_A_LENGTH 0x8000 +# define COREB_L1_DATA_B_LENGTH 0x8000 #endif /* Level 2 Memory */ |