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| author | H. Peter Anvin <hpa@zytor.com> | 2008-09-04 08:08:42 -0700 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2008-09-04 08:08:42 -0700 |
| commit | 7203781c98ad9147564d327de6f6513ad8fc0f4e (patch) | |
| tree | 5c29a2a04a626bf08a0d56fd8a0068b3c92ad284 /arch/blackfin/mach-common/lock.S | |
| parent | 671eef85a3e885dff4ce210d8774ad50a91d5967 (diff) | |
| parent | af2e1f276ff08f17192411ea3b71c13a758dfe12 (diff) | |
| download | linux-7203781c98ad9147564d327de6f6513ad8fc0f4e.tar.gz linux-7203781c98ad9147564d327de6f6513ad8fc0f4e.tar.bz2 linux-7203781c98ad9147564d327de6f6513ad8fc0f4e.zip | |
Merge branch 'x86/cpu' into x86/core
Conflicts:
arch/x86/kernel/cpu/feature_names.c
include/asm-x86/cpufeature.h
Diffstat (limited to 'arch/blackfin/mach-common/lock.S')
| -rw-r--r-- | arch/blackfin/mach-common/lock.S | 45 |
1 files changed, 31 insertions, 14 deletions
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S index 30b887e67dd6..9daf01201e9f 100644 --- a/arch/blackfin/mach-common/lock.S +++ b/arch/blackfin/mach-common/lock.S @@ -28,13 +28,10 @@ */ #include <linux/linkage.h> -#include <asm/cplb.h> #include <asm/blackfin.h> .text -#ifdef CONFIG_BFIN_ICACHE_LOCK - /* When you come here, it is assumed that * R0 - Which way to be locked */ @@ -189,18 +186,38 @@ ENTRY(_cache_lock) RTS; ENDPROC(_cache_lock) -#endif /* BFIN_ICACHE_LOCK */ - -/* Return the ILOC bits of IMEM_CONTROL +/* Invalidate the Entire Instruction cache by + * disabling IMC bit */ +ENTRY(_invalidate_entire_icache) + [--SP] = ( R7:5); -ENTRY(_read_iloc) - P1.H = HI(IMEM_CONTROL); - P1.L = LO(IMEM_CONTROL); - R1 = 0xF; - R0 = [P1]; - R0 = R0 >> 3; - R0 = R0 & R1; + P0.L = LO(IMEM_CONTROL); + P0.H = HI(IMEM_CONTROL); + R7 = [P0]; + + /* Clear the IMC bit , All valid bits in the instruction + * cache are set to the invalid state + */ + BITCLR(R7,IMC_P); + CLI R6; + SSYNC; /* SSYNC required before invalidating cache. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the instruction cache agian */ + R6 = (IMC | ENICPLB); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + ( R7:5) = [SP++]; RTS; -ENDPROC(_read_iloc) +ENDPROC(_invalidate_entire_icache) |