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| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2015-08-03 12:46:38 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2015-08-13 13:20:02 +0200 |
| commit | 4585b000ace6438d0b142746baab658056b223d9 (patch) | |
| tree | 6b2337f12c2c1028386f8280a4db31b2c24084e7 /arch/hexagon/include | |
| parent | 39b87ad166114b842159e5384a948b168cfa61d8 (diff) | |
| download | linux-4585b000ace6438d0b142746baab658056b223d9.tar.gz linux-4585b000ace6438d0b142746baab658056b223d9.tar.bz2 linux-4585b000ace6438d0b142746baab658056b223d9.zip | |
pinctrl: cherryview: Serialize all register access
There is a hardware issue in Intel Braswell/Cherryview where concurrent
GPIO register access might results reads of 0xffffffff and writes might get
dropped.
Prevent this from happening by taking the serializing lock for all places
where it is possible that more than one thread might be accessing the
hardware concurrently.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/hexagon/include')
0 files changed, 0 insertions, 0 deletions