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| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-07 12:34:57 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-07 12:34:57 -0700 |
| commit | a989705c4cf6e6c1a339c95f9daf658b4ba88ca8 (patch) | |
| tree | d1925b831ec9fbae65db1b193dbad1869c43a9bc /arch/ia64/mm/init.c | |
| parent | 2d56d3c43cc97ae48586745556f5a5b564d61582 (diff) | |
| parent | d29182534c5f39ff899763d1e0982d8f33791d6f (diff) | |
| download | linux-a989705c4cf6e6c1a339c95f9daf658b4ba88ca8.tar.gz linux-a989705c4cf6e6c1a339c95f9daf658b4ba88ca8.tar.bz2 linux-a989705c4cf6e6c1a339c95f9daf658b4ba88ca8.zip | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
[IA64] update memory attribute aliasing documentation & test cases
[IA64] fail mmaps that span areas with incompatible attributes
[IA64] allow WB /sys/.../legacy_mem mmaps
[IA64] make ioremap avoid unsupported attributes
[IA64] rename ioremap variables to match i386
[IA64] relax per-cpu TLB requirement to DTC
[IA64] remove per-cpu ia64_phys_stacked_size_p8
[IA64] Fix example error injection program
[IA64] Itanium MC Error Injection Tool: pal_mc_error_inject() interface
[IA64] Itanium MC Error Injection Tool: Makefile changes
[IA64] Itanium MC Error Injection Tool: Driver sysfs interface
[IA64] Itanium MC Error Injection Tool: Doc and sample application
[IA64] Itanium MC Error Injection Tool: Kernel configuration
Diffstat (limited to 'arch/ia64/mm/init.c')
| -rw-r--r-- | arch/ia64/mm/init.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c index 2da841110727..cffb1e8325e8 100644 --- a/arch/ia64/mm/init.c +++ b/arch/ia64/mm/init.c @@ -355,7 +355,7 @@ setup_gate (void) void __devinit ia64_mmu_init (void *my_cpu_data) { - unsigned long psr, pta, impl_va_bits; + unsigned long pta, impl_va_bits; extern void __devinit tlb_init (void); #ifdef CONFIG_DISABLE_VHPT @@ -364,15 +364,6 @@ ia64_mmu_init (void *my_cpu_data) # define VHPT_ENABLE_BIT 1 #endif - /* Pin mapping for percpu area into TLB */ - psr = ia64_clear_ic(); - ia64_itr(0x2, IA64_TR_PERCPU_DATA, PERCPU_ADDR, - pte_val(pfn_pte(__pa(my_cpu_data) >> PAGE_SHIFT, PAGE_KERNEL)), - PERCPU_PAGE_SHIFT); - - ia64_set_psr(psr); - ia64_srlz_i(); - /* * Check if the virtually mapped linear page table (VMLPT) overlaps with a mapped * address space. The IA-64 architecture guarantees that at least 50 bits of |