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| author | Angelo Dureghello <angelo@kernel-space.org> | 2021-04-08 23:37:40 +0200 |
|---|---|---|
| committer | Greg Ungerer <gerg@linux-m68k.org> | 2021-04-23 15:33:40 +1000 |
| commit | 6b3788e5fb8041211ac2fa7c818ca9010e976a74 (patch) | |
| tree | 834900e18f23b09c117a0196fc413c07ab57c6f4 /arch/m68k/coldfire | |
| parent | 09accc3a05f7f1a6486f4a278d209ac122289c0b (diff) | |
| download | linux-6b3788e5fb8041211ac2fa7c818ca9010e976a74.tar.gz linux-6b3788e5fb8041211ac2fa7c818ca9010e976a74.tar.bz2 linux-6b3788e5fb8041211ac2fa7c818ca9010e976a74.zip | |
m68k: coldfire: fix irq ranges
Working on flexcan0, there was no way to have irq 128 working.
Fix irq 128 and 196 setup.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
Diffstat (limited to 'arch/m68k/coldfire')
| -rw-r--r-- | arch/m68k/coldfire/intc-simr.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/m68k/coldfire/intc-simr.c b/arch/m68k/coldfire/intc-simr.c index 15c4b7a6e38f..f7c2c41b3156 100644 --- a/arch/m68k/coldfire/intc-simr.c +++ b/arch/m68k/coldfire/intc-simr.c @@ -68,9 +68,9 @@ static void intc_irq_mask(struct irq_data *d) { unsigned int irq = d->irq - MCFINT_VECBASE; - if (MCFINTC2_SIMR && (irq > 128)) + if (MCFINTC2_SIMR && (irq > 127)) __raw_writeb(irq - 128, MCFINTC2_SIMR); - else if (MCFINTC1_SIMR && (irq > 64)) + else if (MCFINTC1_SIMR && (irq > 63)) __raw_writeb(irq - 64, MCFINTC1_SIMR); else __raw_writeb(irq, MCFINTC0_SIMR); @@ -80,9 +80,9 @@ static void intc_irq_unmask(struct irq_data *d) { unsigned int irq = d->irq - MCFINT_VECBASE; - if (MCFINTC2_CIMR && (irq > 128)) + if (MCFINTC2_CIMR && (irq > 127)) __raw_writeb(irq - 128, MCFINTC2_CIMR); - else if (MCFINTC1_CIMR && (irq > 64)) + else if (MCFINTC1_CIMR && (irq > 63)) __raw_writeb(irq - 64, MCFINTC1_CIMR); else __raw_writeb(irq, MCFINTC0_CIMR); @@ -115,9 +115,9 @@ static unsigned int intc_irq_startup(struct irq_data *d) } irq -= MCFINT_VECBASE; - if (MCFINTC2_ICR0 && (irq > 128)) + if (MCFINTC2_ICR0 && (irq > 127)) __raw_writeb(5, MCFINTC2_ICR0 + irq - 128); - else if (MCFINTC1_ICR0 && (irq > 64)) + else if (MCFINTC1_ICR0 && (irq > 63)) __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); else __raw_writeb(5, MCFINTC0_ICR0 + irq); |