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| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-10 15:22:19 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 15:19:20 +1000 |
| commit | 07ffee59a756e3d16295fa1e0a4849c7a2273a13 (patch) | |
| tree | 07161a81e704f140d1cccd424d9f99df5490908b /arch/m68k/include/asm/m54xxacr.h | |
| parent | 4a5bae416562a8224707a1ff30e83ddab1474fb3 (diff) | |
| download | linux-07ffee59a756e3d16295fa1e0a4849c7a2273a13.tar.gz linux-07ffee59a756e3d16295fa1e0a4849c7a2273a13.tar.bz2 linux-07ffee59a756e3d16295fa1e0a4849c7a2273a13.zip | |
m68knommu: create optimal separate instruction and data cache for ColdFire
Create separate functions to deal with instruction and data cache flushing.
This way we can optimize them for the vairous cache types and arrangements
used across the ColdFire family.
For example the unified caches in the version 3 cores means we don't
need to flush the instruction cache. For the version 2 cores that do
not do data cacheing (or where we choose instruction cache only) we
don't need to do any data flushing.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m54xxacr.h')
| -rw-r--r-- | arch/m68k/include/asm/m54xxacr.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 29d4713f796b..16a1835f9b2a 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -81,15 +81,14 @@ #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) -#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) +#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) #define ACR1_MODE 0 #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) #define ACR3_MODE 0 -#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) -#define flush_dcache_range(a, l) do { asm("nop"); } while (0) -#endif #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) /* Copyback cache mode must push dirty cache lines first */ #define CACHE_PUSH |