diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-10-11 10:55:04 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-10-11 10:55:04 +0100 |
| commit | a0f0dd57f4a85310d9936f1770a0424b49fef876 (patch) | |
| tree | 2f85b8b67dda13d19b02ca39e0fbef921cb1cf8b /arch/m68k/include/asm/m54xxgpt.h | |
| parent | 2a552d5e63d7fa602c9a9a0717008737f55625a6 (diff) | |
| parent | 846a136881b8f73c1f74250bf6acfaa309cab1f2 (diff) | |
| download | linux-a0f0dd57f4a85310d9936f1770a0424b49fef876.tar.gz linux-a0f0dd57f4a85310d9936f1770a0424b49fef876.tar.bz2 linux-a0f0dd57f4a85310d9936f1770a0424b49fef876.zip | |
Merge branch 'fixes' into for-linus
Conflicts:
arch/arm/kernel/smp.c
Diffstat (limited to 'arch/m68k/include/asm/m54xxgpt.h')
| -rw-r--r-- | arch/m68k/include/asm/m54xxgpt.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h index df75dd87ae7a..0b69cd1ed0ed 100644 --- a/arch/m68k/include/asm/m54xxgpt.h +++ b/arch/m68k/include/asm/m54xxgpt.h @@ -16,26 +16,26 @@ *********************************************************************/ /* Register read/write macros */ -#define MCF_GPT_GMS0 0x000800 -#define MCF_GPT_GCIR0 0x000804 -#define MCF_GPT_GPWM0 0x000808 -#define MCF_GPT_GSR0 0x00080C -#define MCF_GPT_GMS1 0x000810 -#define MCF_GPT_GCIR1 0x000814 -#define MCF_GPT_GPWM1 0x000818 -#define MCF_GPT_GSR1 0x00081C -#define MCF_GPT_GMS2 0x000820 -#define MCF_GPT_GCIR2 0x000824 -#define MCF_GPT_GPWM2 0x000828 -#define MCF_GPT_GSR2 0x00082C -#define MCF_GPT_GMS3 0x000830 -#define MCF_GPT_GCIR3 0x000834 -#define MCF_GPT_GPWM3 0x000838 -#define MCF_GPT_GSR3 0x00083C -#define MCF_GPT_GMS(x) (0x000800+((x)*0x010)) -#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010)) -#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010)) -#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010)) +#define MCF_GPT_GMS0 (MCF_MBAR + 0x000800) +#define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804) +#define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808) +#define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C) +#define MCF_GPT_GMS1 (MCF_MBAR + 0x000810) +#define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814) +#define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818) +#define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C) +#define MCF_GPT_GMS2 (MCF_MBAR + 0x000820) +#define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824) +#define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828) +#define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C) +#define MCF_GPT_GMS3 (MCF_MBAR + 0x000830) +#define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834) +#define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838) +#define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C) +#define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010)) +#define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010)) +#define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010)) +#define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010)) /* Bit definitions and macros for MCF_GPT_GMS */ #define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) |