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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-08-24 18:32:49 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-09-07 22:24:27 +0200
commit256ec489f1c7726f0db9ffee88ba7cdc317806cd (patch)
treec144af757fa94627e5c0cd765da9e31d02af5f8a /arch/mips/Kconfig
parent886ee1363a3ad2b890959f07cffe8d91d995b93a (diff)
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MIPS: Convert R10000_LLSC_WAR info a config option
Use a new config option to enabel R1000_LLSC workaound and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/Kconfig')
-rw-r--r--arch/mips/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 5df92ae935d4..87ef000d1aec 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -669,6 +669,7 @@ config SGI_IP27
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
+ select WAR_R10000_LLSC
select MIPS_L1_CACHE_SHIFT_7
select NUMA
help
@@ -704,6 +705,7 @@ config SGI_IP28
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
+ select WAR_R10000_LLSC
select MIPS_L1_CACHE_SHIFT_7
help
This is the SGI Indigo2 with R10000 processor. To compile a Linux
@@ -730,6 +732,7 @@ config SGI_IP30
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_SMP
+ select WAR_R10000_LLSC
select MIPS_L1_CACHE_SHIFT_7
select ARC_MEMORY
help
@@ -2675,6 +2678,11 @@ config WAR_TX49XX_ICACHE_INDEX_INV
config WAR_ICACHE_REFILLS
bool
+# On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
+# may cause ll / sc and lld / scd sequences to execute non-atomically.
+config WAR_R10000_LLSC
+ bool
+
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed