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| author | Manuel Lauss <mano@roarinelk.homelinux.net> | 2008-12-21 09:26:23 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-11 09:57:27 +0000 |
| commit | 0c694de12b54fa96b9555e07603f567906ce21c8 (patch) | |
| tree | c7528273c1d86069cb6e83bd2b36706f663f1eb2 /arch/mips/alchemy/common/setup.c | |
| parent | 779e7d41ad004946603da139da99ba775f74cb1c (diff) | |
| download | linux-0c694de12b54fa96b9555e07603f567906ce21c8.tar.gz linux-0c694de12b54fa96b9555e07603f567906ce21c8.tar.bz2 linux-0c694de12b54fa96b9555e07603f567906ce21c8.zip | |
MIPS: Alchemy: RTC counter clocksource / clockevent support.
Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent
device. As a nice side effect, this also enables use of the 'wait'
instruction for runtime idle power savings.
If the counters aren't enabled/working properly, fall back on the
cp0 counter clock code.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/common/setup.c')
| -rw-r--r-- | arch/mips/alchemy/common/setup.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 4d42be811e7f..8ad453af2c64 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -63,12 +63,6 @@ void __init plat_mem_setup(void) ioport_resource.end = IOPORT_RESOURCE_END; iomem_resource.start = IOMEM_RESOURCE_START; iomem_resource.end = IOMEM_RESOURCE_END; - - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); - au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); - au_sync(); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); - au_writel(0, SYS_TOYTRIM); } #if defined(CONFIG_64BIT_PHYS_ADDR) |