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| author | Wu Zhangjin <wuzhangjin@gmail.com> | 2009-07-02 23:26:08 +0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-09-17 20:07:47 +0200 |
| commit | 8e4971175acc910eb4258df82a6bd8f2c4e4e5b5 (patch) | |
| tree | 921d53308d0a8a8e9119ec6b262a01fe0ccd1fd5 /arch/mips/include/asm/mach-loongson/war.h | |
| parent | 67b35e5d01aba7a83f2161b0c90acb08afa01e3e (diff) | |
| download | linux-8e4971175acc910eb4258df82a6bd8f2c4e4e5b5.tar.gz linux-8e4971175acc910eb4258df82a6bd8f2c4e4e5b5.tar.bz2 linux-8e4971175acc910eb4258df82a6bd8f2c4e4e5b5.zip | |
MIPS: Loongson: Change naming methods
To make source code of loongson sharable to the machines(such as gdium)
made by the other companies, we rename arch/mips/lemote to
arch/mips/loongson, asm/mach-lemote to asm/mach-loongson, and rename lm2e
to the name of the machine: fuloong-2e. accordingly, FULONG are renamed to
FULOONG2E to make it distinguishable to the future FULOONG2F. and also,
some other relative tuning is needed.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-loongson/war.h')
| -rw-r--r-- | arch/mips/include/asm/mach-loongson/war.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-loongson/war.h b/arch/mips/include/asm/mach-loongson/war.h new file mode 100644 index 000000000000..4b971c3ffd8d --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MACH_LOONGSON_WAR_H +#define __ASM_MACH_LOONGSON_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_LEMOTE_WAR_H */ |