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| author | David Daney <ddaney@caviumnetworks.com> | 2010-10-07 16:03:40 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-10-29 19:08:33 +0100 |
| commit | aa32a955ae46d4117e880417c89a2efcc88579c2 (patch) | |
| tree | 538f1564b70d017b224a423d99bc2a0366c1f745 /arch/mips/include/asm/octeon/cvmx-led-defs.h | |
| parent | b93b2abce497873be97d765b848e0a955d29f200 (diff) | |
| download | linux-aa32a955ae46d4117e880417c89a2efcc88579c2.tar.gz linux-aa32a955ae46d4117e880417c89a2efcc88579c2.tar.bz2 linux-aa32a955ae46d4117e880417c89a2efcc88579c2.zip | |
MIPS: Octeon: Update register definitions for CN63XX chips
The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.
Join some lines back together. This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-led-defs.h')
| -rw-r--r-- | arch/mips/include/asm/octeon/cvmx-led-defs.h | 41 |
1 files changed, 14 insertions, 27 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h index 16f174a4dadf..e25173bb8bb7 100644 --- a/arch/mips/include/asm/octeon/cvmx-led-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,32 +28,19 @@ #ifndef __CVMX_LED_DEFS_H__ #define __CVMX_LED_DEFS_H__ -#define CVMX_LED_BLINK \ - CVMX_ADD_IO_SEG(0x0001180000001A48ull) -#define CVMX_LED_CLK_PHASE \ - CVMX_ADD_IO_SEG(0x0001180000001A08ull) -#define CVMX_LED_CYLON \ - CVMX_ADD_IO_SEG(0x0001180000001AF8ull) -#define CVMX_LED_DBG \ - CVMX_ADD_IO_SEG(0x0001180000001A18ull) -#define CVMX_LED_EN \ - CVMX_ADD_IO_SEG(0x0001180000001A00ull) -#define CVMX_LED_POLARITY \ - CVMX_ADD_IO_SEG(0x0001180000001A50ull) -#define CVMX_LED_PRT \ - CVMX_ADD_IO_SEG(0x0001180000001A10ull) -#define CVMX_LED_PRT_FMT \ - CVMX_ADD_IO_SEG(0x0001180000001A30ull) -#define CVMX_LED_PRT_STATUSX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8)) -#define CVMX_LED_UDD_CNTX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8)) -#define CVMX_LED_UDD_DATX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8)) -#define CVMX_LED_UDD_DAT_CLRX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16)) -#define CVMX_LED_UDD_DAT_SETX(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16)) +#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull)) +#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull)) +#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull)) +#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull)) +#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull)) +#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull)) +#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull)) +#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull)) +#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8) +#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8) +#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8) +#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16) +#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16) union cvmx_led_blink { uint64_t u64; |