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authorFlorian Fainelli <florian@openwrt.org>2008-10-31 14:24:29 +0100
committerRalf Baechle <ralf@linux-mips.org>2008-11-20 19:42:32 +0000
commit1b432840d0a4740020e29ae7a00717ef8f44954b (patch)
tree64374760eb188224bba02321bba49b99eeff4dc6 /arch/mips/include
parent9e86786a4b17ad186f456dc6ac0508a17556731b (diff)
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MIPS: RB532: GPIO register offsets are relative to GPIOBASE
This patch fixes the wrong use of GPIO register offsets in devices.c. To avoid further problems, use gpio_get_value to return the NAND status instead of our own expanded code. Also define the zero offset of the alternate function register to allow consistent access. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Phil Sutter <n0-1@freewrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/mach-rc32434/rb.h14
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index 79e8ef67d0d3..f25a84916703 100644
--- a/arch/mips/include/asm/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -40,12 +40,14 @@
#define BTCS 0x010040
#define BTCOMPARE 0x010044
#define GPIOBASE 0x050000
-#define GPIOCFG 0x050004
-#define GPIOD 0x050008
-#define GPIOILEVEL 0x05000C
-#define GPIOISTAT 0x050010
-#define GPIONMIEN 0x050014
-#define IMASK6 0x038038
+/* Offsets relative to GPIOBASE */
+#define GPIOFUNC 0x00
+#define GPIOCFG 0x04
+#define GPIOD 0x08
+#define GPIOILEVEL 0x0C
+#define GPIOISTAT 0x10
+#define GPIONMIEN 0x14
+#define IMASK6 0x38
#define LO_WPX (1 << 0)
#define LO_ALE (1 << 1)
#define LO_CLE (1 << 2)