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| author | David Daney <ddaney@caviumnetworks.com> | 2008-12-11 15:33:29 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-11 09:57:22 +0000 |
| commit | 8faca49a6731299c32b333fd6535db8d21557ce3 (patch) | |
| tree | d1e571f644d58f2ffac4bd538750dc95b8c0bb79 /arch/mips/include | |
| parent | 7e69deb83c9fffe75e8ea17fb40a63375e56ac9f (diff) | |
| download | linux-8faca49a6731299c32b333fd6535db8d21557ce3.tar.gz linux-8faca49a6731299c32b333fd6535db8d21557ce3.tar.bz2 linux-8faca49a6731299c32b333fd6535db8d21557ce3.zip | |
MIPS: Modify core io.h macros to account for the Octeon Errata Core-301.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/io.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 501a40b9f18d..436878e4e063 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -295,6 +295,12 @@ static inline void iounmap(const volatile void __iomem *addr) #undef __IS_KSEG1 } +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define war_octeon_io_reorder_wmb() wmb() +#else +#define war_octeon_io_reorder_wmb() do { } while (0) +#endif + #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ \ static inline void pfx##write##bwlq(type val, \ @@ -303,6 +309,8 @@ static inline void pfx##write##bwlq(type val, \ volatile type *__mem; \ type __val; \ \ + war_octeon_io_reorder_wmb(); \ + \ __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ \ __val = pfx##ioswab##bwlq(__mem, val); \ @@ -370,6 +378,8 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \ volatile type *__addr; \ type __val; \ \ + war_octeon_io_reorder_wmb(); \ + \ __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ \ __val = pfx##ioswab##bwlq(__addr, val); \ @@ -504,8 +514,12 @@ BUILDSTRING(q, u64) #endif +#ifdef CONFIG_CPU_CAVIUM_OCTEON +#define mmiowb() wmb() +#else /* Depends on MIPS II instruction set */ #define mmiowb() asm volatile ("sync" ::: "memory") +#endif static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) { |