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| author | Paul Burton <paul.burton@imgtec.com> | 2015-05-24 16:11:30 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-06-21 21:53:07 +0200 |
| commit | 24ccfa06b7ea3c3f7f53f6bac9425d604ebce470 (patch) | |
| tree | c96b4f1939354ea8eb0787e340669116390377dc /arch/mips/jz4740 | |
| parent | 2da018849fc79da116970c30e99a6ff216eaee47 (diff) | |
| download | linux-24ccfa06b7ea3c3f7f53f6bac9425d604ebce470.tar.gz linux-24ccfa06b7ea3c3f7f53f6bac9425d604ebce470.tar.bz2 linux-24ccfa06b7ea3c3f7f53f6bac9425d604ebce470.zip | |
MIPS: JZ4740: support newer SoC interrupt controllers
Allow the interrupt controllers of the JZ4770, JZ4775 & JZ4780 SoCs to
be probed via devicetree, supporting the 64 interrupts they provide.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Brian Norris <computersforpeace@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/10155/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/jz4740')
| -rw-r--r-- | arch/mips/jz4740/irq.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c index 5887f379ff6e..64b4c3639280 100644 --- a/arch/mips/jz4740/irq.c +++ b/arch/mips/jz4740/irq.c @@ -167,3 +167,12 @@ static int __init intc_1chip_of_init(struct device_node *node, return ingenic_intc_of_init(node, 1); } IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init); + +static int __init intc_2chip_of_init(struct device_node *node, + struct device_node *parent) +{ + return ingenic_intc_of_init(node, 2); +} +IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); +IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); +IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); |