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| author | Paul Burton <paul.burton@imgtec.com> | 2017-06-02 11:35:01 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-06-15 11:47:42 +0200 |
| commit | 1a73d9310e093fc3adffba4d0a67b9fab2ee3f63 (patch) | |
| tree | 82140dccc098d00836472543a6a645fe92d0f804 /arch/mips/kernel/branch.c | |
| parent | 698b851073ddf5a894910d63ca04605e0473414e (diff) | |
| download | linux-1a73d9310e093fc3adffba4d0a67b9fab2ee3f63.tar.gz linux-1a73d9310e093fc3adffba4d0a67b9fab2ee3f63.tar.bz2 linux-1a73d9310e093fc3adffba4d0a67b9fab2ee3f63.zip | |
MIPS: Fix bnezc/jialc return address calculation
The code handling the pop76 opcode (ie. bnezc & jialc instructions) in
__compute_return_epc_for_insn() needs to set the value of $31 in the
jialc case, which is encoded with rs = 0. However its check to
differentiate bnezc (rs != 0) from jialc (rs = 0) was unfortunately
backwards, meaning that if we emulate a bnezc instruction we clobber $31
& if we emulate a jialc instruction it actually behaves like a jic
instruction.
Fix this by inverting the check of rs to match the way the instructions
are actually encoded.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 28d6f93d201d ("MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions")
Cc: stable <stable@vger.kernel.org> # v4.0+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16178/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/branch.c')
| -rw-r--r-- | arch/mips/kernel/branch.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index b11facd11c9d..f702a459a830 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -804,8 +804,10 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, break; } /* Compact branch: BNEZC || JIALC */ - if (insn.i_format.rs) + if (!insn.i_format.rs) { + /* JIALC: set $31/ra */ regs->regs[31] = epc + 4; + } regs->cp0_epc += 8; break; #endif |