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| author | Paul Burton <paul.burton@imgtec.com> | 2014-01-15 10:31:53 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-26 23:00:12 +0100 |
| commit | 0ee958e102b62b418c2fb46c3439d4262067a5fc (patch) | |
| tree | e69192dc3112657cdde015ea8a43594a41a24d89 /arch/mips/kernel/cpu-probe.c | |
| parent | b86c2247a20f5d8b6f2b3bd0dfd2c9c8c6908b5e (diff) | |
| download | linux-0ee958e102b62b418c2fb46c3439d4262067a5fc.tar.gz linux-0ee958e102b62b418c2fb46c3439d4262067a5fc.tar.bz2 linux-0ee958e102b62b418c2fb46c3439d4262067a5fc.zip | |
MIPS: Coherent Processing System SMP implementation
This patch introduces a new SMP implementation for systems implementing
the MIPS Coherent Processing System architecture. The kernel will make
use of the Coherence Manager, Cluster Power Controller & Global
Interrupt Controller in order to detect, bring up & make use of other
cores in the system. SMTC is not supported, so only a single TC per VPE
in the system is used. That is, this option enables an SMVP style setup
but across multiple cores.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6362/
Patchwork: https://patchwork.linux-mips.org/patch/6611/
Patchwork: https://patchwork.linux-mips.org/patch/6651/
Patchwork: https://patchwork.linux-mips.org/patch/6652/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index ac09248b7468..c1ee8b4d2144 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -398,8 +398,10 @@ static void decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); +#ifndef CONFIG_MIPS_CPS if (cpu_has_mips_r2) c->core = read_c0_ebase() & 0x3ff; +#endif } #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |