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authorAl Cooper <alcooperx@gmail.com>2012-07-13 16:44:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-10-11 11:04:34 +0200
commitda4b62cd6762ce327f660c6e45c8d5a739197159 (patch)
tree7cbb0b1ce047c514f92da5ef382ca0bc6002cf21 /arch/mips/kernel/cpu-probe.c
parentc5600b2dd9fc7318feddf69f127ca793437c714d (diff)
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MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)
The PCI (Program Counter Interrupt) bit in the "cause" register is mandatory for MIPS32R2 cores, but has also been added to some R1 cores (BMIPS5000). This change adds a cpu feature bit to make it easier to check for and use this feature. Signed-off-by: Al Cooper <alcooperx@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r--arch/mips/kernel/cpu-probe.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bc58bd10a607..bd2809698e39 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1194,8 +1194,11 @@ __cpuinit void cpu_probe(void)
}
}
- if (cpu_has_mips_r2)
+ if (cpu_has_mips_r2) {
c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
+ /* R2 has Performance Counter Interrupt indicator */
+ c->options |= MIPS_CPU_PCI;
+ }
else
c->srsets = 1;