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| author | Ralf Baechle <ralf@linux-mips.org> | 2014-04-30 11:21:55 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-05-23 15:12:38 +0200 |
| commit | 56a6473339dbd2e908cf8c6f2856d5de2bf8d15b (patch) | |
| tree | a500f42c8e140cd909d0a5340474f6012c0740b4 /arch/mips/math-emu/dp_sqrt.c | |
| parent | aef3fb76aa1390ef864db888d06d8fcd5510df2d (diff) | |
| download | linux-56a6473339dbd2e908cf8c6f2856d5de2bf8d15b.tar.gz linux-56a6473339dbd2e908cf8c6f2856d5de2bf8d15b.tar.bz2 linux-56a6473339dbd2e908cf8c6f2856d5de2bf8d15b.zip | |
MIPS: math-emu: Switch to using the MIPS rounding modes.
Previously math-emu was using the IEEE-754 constants internally. These
were differing by having the constants for rounding to +/- infinity
switched, so a conversion was necessary. This would be entirely
avoidable if the MIPS constants were used throughout, so get rid of
the bloat.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/math-emu/dp_sqrt.c')
| -rw-r--r-- | arch/mips/math-emu/dp_sqrt.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c index 0384c094b1aa..041bbb6124bb 100644 --- a/arch/mips/math-emu/dp_sqrt.c +++ b/arch/mips/math-emu/dp_sqrt.c @@ -80,7 +80,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x) oldcsr = ieee754_csr; ieee754_csr.mx &= ~IEEE754_INEXACT; ieee754_csr.sx &= ~IEEE754_INEXACT; - ieee754_csr.rm = IEEE754_RN; + ieee754_csr.rm = FPU_CSR_RN; /* adjust exponent to prevent overflow */ scalx = 0; @@ -122,7 +122,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x) /* twiddle last bit to force y correctly rounded */ /* set RZ, clear INEX flag */ - ieee754_csr.rm = IEEE754_RZ; + ieee754_csr.rm = FPU_CSR_RZ; ieee754_csr.sx &= ~IEEE754_INEXACT; /* t=x/y; ...chopped quotient, possibly inexact */ @@ -139,10 +139,10 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x) oldcsr.sx |= IEEE754_INEXACT; switch (oldcsr.rm) { - case IEEE754_RU: + case FPU_CSR_RU: y.bits += 1; /* drop through */ - case IEEE754_RN: + case FPU_CSR_RN: t.bits += 1; break; } |