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author | Markos Chandras <markos.chandras@imgtec.com> | 2015-08-13 09:56:34 +0200 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2015-09-03 12:08:14 +0200 |
commit | 38db37ba069f9d801ef56b820cfc7c247a7ffc02 (patch) | |
tree | 9a053440a3afabd7f7f19bcc65a9cd9d0735f028 /arch/mips/math-emu/sp_2008class.c | |
parent | 400bd2e41393a783e0532321fdb369d2cc15ea26 (diff) | |
download | linux-38db37ba069f9d801ef56b820cfc7c247a7ffc02.tar.gz linux-38db37ba069f9d801ef56b820cfc7c247a7ffc02.tar.bz2 linux-38db37ba069f9d801ef56b820cfc7c247a7ffc02.zip |
MIPS: math-emu: Add support for the MIPS R6 CLASS FPU instruction
MIPS R6 introduced the following instruction:
Stores in fd a bit mask reflecting the floating-point class of the
floating point scalar value fs.
CLASS.fmt: FPR[fd] = class(FPR[fs])
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10959/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/math-emu/sp_2008class.c')
-rw-r--r-- | arch/mips/math-emu/sp_2008class.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/arch/mips/math-emu/sp_2008class.c b/arch/mips/math-emu/sp_2008class.c new file mode 100644 index 000000000000..ff62606a1465 --- /dev/null +++ b/arch/mips/math-emu/sp_2008class.c @@ -0,0 +1,55 @@ +/* + * IEEE754 floating point arithmetic + * single precision: CLASS.f + * FPR[fd] = class(FPR[fs]) + * + * MIPS floating point support + * Copyright (C) 2015 Imagination Technologies, Ltd. + * Author: Markos Chandras <markos.chandras@imgtec.com> + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; version 2 of the License. + */ + +#include "ieee754sp.h" + +int ieee754sp_2008class(union ieee754sp x) +{ + COMPXSP; + + EXPLODEXSP; + + /* + * 10 bit mask as follows: + * + * bit0 = SNAN + * bit1 = QNAN + * bit2 = -INF + * bit3 = -NORM + * bit4 = -DNORM + * bit5 = -ZERO + * bit6 = INF + * bit7 = NORM + * bit8 = DNORM + * bit9 = ZERO + */ + + switch(xc) { + case IEEE754_CLASS_SNAN: + return 0x01; + case IEEE754_CLASS_QNAN: + return 0x02; + case IEEE754_CLASS_INF: + return 0x04 << (xs ? 0 : 4); + case IEEE754_CLASS_NORM: + return 0x08 << (xs ? 0 : 4); + case IEEE754_CLASS_DNORM: + return 0x10 << (xs ? 0 : 4); + case IEEE754_CLASS_ZERO: + return 0x20 << (xs ? 0 : 4); + default: + pr_err("Unknown class: %d\n", xc); + return 0; + } +} |