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author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2007-11-26 23:40:01 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2008-01-29 10:14:57 +0000 |
commit | e9c33572a92aa2ee565da5136745ea304ac23d9a (patch) | |
tree | c2a56008c9205540438352363fbcfea593019741 /arch/mips/mm/c-r4k.c | |
parent | 87353d8ac39c52784da605ecbe965ecdfad609ad (diff) | |
download | linux-e9c33572a92aa2ee565da5136745ea304ac23d9a.tar.gz linux-e9c33572a92aa2ee565da5136745ea304ac23d9a.tar.bz2 linux-e9c33572a92aa2ee565da5136745ea304ac23d9a.zip |
[MIPS] Use real cache invalidate
R10k non coherent machines need a real dma cache invalidate to get rid of
speculative stores in cache. For other machines this promises a slight
speedup.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r-- | arch/mips/mm/c-r4k.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c91b59680695..06074948450d 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -589,7 +589,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) if (size >= scache_size) r4k_blast_scache(); else - blast_scache_range(addr, addr + size); + blast_inv_scache_range(addr, addr + size); return; } @@ -597,7 +597,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) r4k_blast_dcache(); } else { R4600_HIT_CACHEOP_WAR_IMPL; - blast_dcache_range(addr, addr + size); + blast_inv_dcache_range(addr, addr + size); } bc_inv(addr, size); |