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authorThomas Gleixner <tglx@linutronix.de>2010-02-17 18:27:37 +0100
committerThomas Gleixner <tglx@linutronix.de>2010-02-17 18:28:05 +0100
commitb7e56edba4b02f2079042c326a8cd72a44635817 (patch)
treeb5042002e9747cd8fb1278d61f86d8b92a74c018 /arch/mips/mm
parent13ca0fcaa33f6b1984c4111b6ec5df42689fea6f (diff)
parentb0483e78e5c4c9871fc5541875b3bc006846d46b (diff)
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Merge branch 'linus' into x86/mm
x86/mm is on 32-rc4 and missing the spinlock namespace changes which are needed for further commits into this topic. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/c-octeon.c4
-rw-r--r--arch/mips/mm/cache.c4
-rw-r--r--arch/mips/mm/cerr-sb1.c7
-rw-r--r--arch/mips/mm/dma-default.c7
-rw-r--r--arch/mips/mm/init.c10
-rw-r--r--arch/mips/mm/tlbex.c36
-rw-r--r--arch/mips/mm/uasm.c16
-rw-r--r--arch/mips/mm/uasm.h7
8 files changed, 66 insertions, 25 deletions
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 94e05e5733c1..e06f1af760a7 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -174,7 +174,7 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma,
* Probe Octeon's caches
*
*/
-static void __devinit probe_octeon(void)
+static void __cpuinit probe_octeon(void)
{
unsigned long icache_size;
unsigned long dcache_size;
@@ -235,7 +235,7 @@ static void __devinit probe_octeon(void)
* Setup the Octeon cache flush routines
*
*/
-void __devinit octeon_cache_init(void)
+void __cpuinit octeon_cache_init(void)
{
extern unsigned long ebase;
extern char except_vec2_octeon;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 694d51f523d1..e716cafc346d 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -155,7 +155,7 @@ static inline void setup_protection_map(void)
protection_map[15] = PAGE_SHARED;
}
-void __devinit cpu_cache_init(void)
+void __cpuinit cpu_cache_init(void)
{
if (cpu_has_3k_cache) {
extern void __weak r3k_cache_init(void);
@@ -194,7 +194,7 @@ void __devinit cpu_cache_init(void)
int __weak __uncached_access(struct file *file, unsigned long addr)
{
- if (file->f_flags & O_SYNC)
+ if (file->f_flags & O_DSYNC)
return 1;
return addr >= __pa(high_memory);
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 1bd1f18ac23c..3571090ba178 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -567,13 +567,10 @@ static uint32_t extract_dc(unsigned short addr, int data)
datalo = ((unsigned long long)datalohi << 32) | datalolo;
ecc = dc_ecc(datalo);
if (ecc != datahi) {
- int bits = 0;
+ int bits;
bad_ecc |= 1 << (3-offset);
ecc ^= datahi;
- while (ecc) {
- if (ecc & 1) bits++;
- ecc >>= 1;
- }
+ bits = hweight8(ecc);
res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
}
printk(" %02X-%016llX", datahi, datalo);
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 7e48e76148aa..9367e33fbd18 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -90,6 +90,9 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
{
void *ret;
+ if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
+ return ret;
+
gfp = massage_gfp_flags(dev, gfp);
ret = (void *) __get_free_pages(gfp, get_order(size));
@@ -122,6 +125,10 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle)
{
unsigned long addr = (unsigned long) vaddr;
+ int order = get_order(size);
+
+ if (dma_release_from_coherent(dev, order, vaddr))
+ return;
plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 4d72aabe8352..dee564aad23a 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -27,6 +27,7 @@
#include <linux/swap.h>
#include <linux/proc_fs.h>
#include <linux/pfn.h>
+#include <linux/hardirq.h>
#include <asm/asm-offsets.h>
#include <asm/bootinfo.h>
@@ -132,7 +133,10 @@ void *kmap_coherent(struct page *page, unsigned long addr)
inc_preempt_count();
idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
#ifdef CONFIG_MIPS_MT_SMTC
- idx += FIX_N_COLOURS * smp_processor_id();
+ idx += FIX_N_COLOURS * smp_processor_id() +
+ (in_interrupt() ? (FIX_N_COLOURS * NR_CPUS) : 0);
+#else
+ idx += in_interrupt() ? FIX_N_COLOURS : 0;
#endif
vaddr = __fix_to_virt(FIX_CMAP_END - idx);
pte = mk_pte(page, PAGE_KERNEL);
@@ -420,7 +424,7 @@ void __init mem_init(void)
reservedpages << (PAGE_SHIFT-10),
datasize >> 10,
initsize >> 10,
- (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
+ totalhigh_pages << (PAGE_SHIFT-10));
}
#endif /* !CONFIG_NEED_MULTIPLE_NODES */
@@ -458,7 +462,9 @@ void __init_refok free_initmem(void)
__pa_symbol(&__init_end));
}
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
unsigned long pgd_current[NR_CPUS];
+#endif
/*
* On 64-bit we've got three-level pagetables with a slightly
* different layout ...
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index bb1719a55d22..badcf5e8d695 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -73,9 +73,6 @@ static int __cpuinit m4kc_tlbp_war(void)
enum label_id {
label_second_part = 1,
label_leave,
-#ifdef MODULE_START
- label_module_alloc,
-#endif
label_vmalloc,
label_vmalloc_done,
label_tlbw_hazard,
@@ -92,9 +89,6 @@ enum label_id {
UASM_L_LA(_second_part)
UASM_L_LA(_leave)
-#ifdef MODULE_START
-UASM_L_LA(_module_alloc)
-#endif
UASM_L_LA(_vmalloc)
UASM_L_LA(_vmalloc_done)
UASM_L_LA(_tlbw_hazard)
@@ -160,6 +154,12 @@ static u32 tlb_handler[128] __cpuinitdata;
static struct uasm_label labels[128] __cpuinitdata;
static struct uasm_reloc relocs[128] __cpuinitdata;
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
+/*
+ * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
+ * we cannot do r3000 under these circumstances.
+ */
+
/*
* The R3000 TLB handler is simple.
*/
@@ -199,6 +199,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
dump_handler((u32 *)ebase, 32);
}
+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
/*
* The R4000 TLB handler is much more complicated. We have two
@@ -497,8 +498,9 @@ static void __cpuinit
build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
unsigned int tmp, unsigned int ptr)
{
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
long pgdc = (long)pgd_current;
-
+#endif
/*
* The vmalloc handling is not in the hotpath.
*/
@@ -506,7 +508,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
uasm_il_bltz(p, r, tmp, label_vmalloc);
/* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
-#ifdef CONFIG_SMP
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
+ /*
+ * &pgd << 11 stored in CONTEXT [23..63].
+ */
+ UASM_i_MFC0(p, ptr, C0_CONTEXT);
+ uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
+ uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
+ uasm_i_drotr(p, ptr, ptr, 11);
+#elif defined(CONFIG_SMP)
# ifdef CONFIG_MIPS_MT_SMTC
/*
* SMTC uses TCBind value as "CPU" index
@@ -520,7 +530,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
*/
uasm_i_dmfc0(p, ptr, C0_CONTEXT);
uasm_i_dsrl(p, ptr, ptr, 23);
-#endif
+# endif
UASM_i_LA_mostly(p, tmp, pgdc);
uasm_i_daddu(p, ptr, ptr, tmp);
uasm_i_dmfc0(p, tmp, C0_BADVADDR);
@@ -802,8 +812,6 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
} else {
#if defined(CONFIG_HUGETLB_PAGE)
const enum label_id ls = label_tlb_huge_update;
-#elif defined(MODULE_START)
- const enum label_id ls = label_module_alloc;
#else
const enum label_id ls = label_vmalloc;
#endif
@@ -1033,6 +1041,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
iPTE_LW(p, pte, ptr);
}
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
/*
* R3000 style TLB load/store/modify handlers.
*/
@@ -1184,6 +1193,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
}
+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
/*
* R4000 style TLB load/store/modify handlers.
@@ -1400,6 +1410,7 @@ void __cpuinit build_tlb_refill_handler(void)
case CPU_TX3912:
case CPU_TX3922:
case CPU_TX3927:
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
build_r3000_tlb_refill_handler();
if (!run_once) {
build_r3000_tlb_load_handler();
@@ -1407,6 +1418,9 @@ void __cpuinit build_tlb_refill_handler(void)
build_r3000_tlb_modify_handler();
run_once++;
}
+#else
+ panic("No R3000 TLB refill handler");
+#endif
break;
case CPU_R6000:
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index f467199676a8..0a165c5179a1 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -60,11 +60,11 @@ enum opcode {
insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
- insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr,
- insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
+ insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
+ insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
- insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori
+ insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
};
struct insn {
@@ -104,6 +104,7 @@ static struct insn insn_table[] __cpuinitdata = {
{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
+ { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
{ insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
@@ -132,6 +133,7 @@ static struct insn insn_table[] __cpuinitdata = {
{ insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
{ insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
+ { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
{ insn_invalid, 0, 0 }
};
@@ -304,6 +306,12 @@ Ip_u2u1s3(op) \
build_insn(buf, insn##op, b, a, c); \
}
+#define I_u2u1msbu3(op) \
+Ip_u2u1msbu3(op) \
+{ \
+ build_insn(buf, insn##op, b, a, c+d-1, c); \
+}
+
#define I_u1u2(op) \
Ip_u1u2(op) \
{ \
@@ -349,6 +357,7 @@ I_u2u1u3(_dsll32)
I_u2u1u3(_dsra)
I_u2u1u3(_dsrl)
I_u2u1u3(_dsrl32)
+I_u2u1u3(_drotr)
I_u3u1u2(_dsubu)
I_0(_eret)
I_u1(_j)
@@ -377,6 +386,7 @@ I_0(_tlbwi)
I_0(_tlbwr)
I_u3u1u2(_xor)
I_u2u1u3(_xori)
+I_u2u1msbu3(_dins);
/* Handle labels. */
void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
index c6d1e3dd82d4..3d153edaa51e 100644
--- a/arch/mips/mm/uasm.h
+++ b/arch/mips/mm/uasm.h
@@ -34,6 +34,11 @@ uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
void __cpuinit \
uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
+#define Ip_u2u1msbu3(op) \
+void __cpuinit \
+uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
+ unsigned int d)
+
#define Ip_u1u2(op) \
void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
@@ -65,6 +70,7 @@ Ip_u2u1u3(_dsll32);
Ip_u2u1u3(_dsra);
Ip_u2u1u3(_dsrl);
Ip_u2u1u3(_dsrl32);
+Ip_u2u1u3(_drotr);
Ip_u3u1u2(_dsubu);
Ip_0(_eret);
Ip_u1(_j);
@@ -93,6 +99,7 @@ Ip_0(_tlbwi);
Ip_0(_tlbwr);
Ip_u3u1u2(_xor);
Ip_u2u1u3(_xori);
+Ip_u2u1msbu3(_dins);
/* Handle labels. */
struct uasm_label {