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| author | Aaro Koskinen <aaro.koskinen@iki.fi> | 2013-07-25 20:26:48 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-08-26 15:31:54 +0200 |
| commit | d8b74276f5488d64ebb28d77631b536f1c5de6d2 (patch) | |
| tree | 14d0ab528fbb73443ae94b9ab84700c78936c067 /arch/mips/pci | |
| parent | 83eefabf9b596b8237cdcc385bff67f70d1e5a2d (diff) | |
| download | linux-d8b74276f5488d64ebb28d77631b536f1c5de6d2.tar.gz linux-d8b74276f5488d64ebb28d77631b536f1c5de6d2.tar.bz2 linux-d8b74276f5488d64ebb28d77631b536f1c5de6d2.zip | |
MIPS: cavium-octeon: fix I/O space setup on non-PCI systems
Fix I/O space setup, so that on non-PCI systems using inb()/outb()
won't crash the system. Some drivers may try to probe I/O space and for
that purpose we can just allocate some normal memory initially. Drivers
trying to reserve a region will fail early as we set the size to 0. If
a real I/O space is present, the PCI/PCIe support code will re-adjust
the values accordingly.
Tested with EdgeRouter Lite by enabling CONFIG_SERIO_I8042 that caused
the originally reported crash.
Reported-by: Faidon Liambotis <paravoid@debian.org>
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5626/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
| -rw-r--r-- | arch/mips/pci/pci-octeon.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 95c2ea815cac..59cccd95688b 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -586,15 +586,16 @@ static int __init octeon_pci_setup(void) else octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; - /* PCI I/O and PCI MEM values */ - set_io_port_base(OCTEON_PCI_IOSPACE_BASE); - ioport_resource.start = 0; - ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; if (!octeon_is_pci_host()) { pr_notice("Not in host mode, PCI Controller not initialized\n"); return 0; } + /* PCI I/O and PCI MEM values */ + set_io_port_base(OCTEON_PCI_IOSPACE_BASE); + ioport_resource.start = 0; + ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; + pr_notice("%s Octeon big bar support\n", (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); |