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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-08-22 11:57:14 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-09-03 23:22:16 +0200 |
| commit | 70c3c4cd2d8ad44231da50830234d3f5e5170613 (patch) | |
| tree | 2de369c6aa848dd57e77d138569dba7c978a0a37 /arch/mips/pci | |
| parent | 9d9a49ab32e8013e2a438a18f17641b4e36bfff2 (diff) | |
| download | linux-70c3c4cd2d8ad44231da50830234d3f5e5170613.tar.gz linux-70c3c4cd2d8ad44231da50830234d3f5e5170613.tar.bz2 linux-70c3c4cd2d8ad44231da50830234d3f5e5170613.zip | |
MIPS: ath79: Don't hardwire cpu_has_dsp{2} to 0
The ath79 code supports various SoCs which are using either a 24Kc
or a 74Kc core. The 74Kc core has DSP support, so don't hardwire
the values to zero.
Commit 00dc5ce2a653a332190aa29b2e1f3bceaa7d5b8d (MIPS: ath79: don't
hardcode the unavailability of the DSP ASE) has fixed this already,
but that change got reverted by 475032564ed96c94c085e3e7a90e07d150a7cec9
(MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.)
Reported-by: Helmut Schaa <helmut.schaa@googlemail.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5750/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
0 files changed, 0 insertions, 0 deletions