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authorRalf Baechle <ralf@linux-mips.org>2007-03-13 13:37:17 +0000
committerRalf Baechle <ralf@linux-mips.org>2007-03-13 16:59:31 +0000
commitaea0e582d3ed9fa966c60b41871381e7f734adf2 (patch)
tree208c3ce7ebf7f81ef1203b866ac1da6ffb945f13 /arch/mips/philips
parent795a22583ba11deb82d57dd70632c7ac390bb8c8 (diff)
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[MIPS] Viper2: Remove defective support.
A defconfig file and the 10 lines of code (including comments ...) that are rotting since lmo commit 6516a42dc8b40c6c00010346dd51496125b16644 don't quite make proper support, so let's trash it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/philips')
-rw-r--r--arch/mips/philips/pnx8550/common/int.c14
1 files changed, 1 insertions, 13 deletions
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index d48665ebd33c..b1c4805a0b92 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -204,19 +204,7 @@ void __init arch_init_irq(void)
* Note, PCI INTA is active low on the bus, but inverted
* in the GIC, so to us it's active high.
*/
-#ifdef CONFIG_PNX8550_V2PCI
- if (gic_int_line == (PNX8550_INT_GPIO0 - PNX8550_INT_GIC_MIN)) {
- /* PCI INT through gpio 8, which is setup in
- * pnx8550_setup.c and routed to GPIO
- * Interrupt Level 0 (GPIO Connection 58).
- * Set it active low. */
-
- PNX8550_GIC_REQ(gic_int_line) = 0x1E020000;
- } else
-#endif
- {
- PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
- }
+ PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
/* mask/priority is still 0 so we will not get any
* interrupts until it is unmasked */