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author | Ralf Baechle <ralf@linux-mips.org> | 2007-07-17 18:49:48 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-20 18:57:39 +0100 |
commit | 5a81299928f3d9abfaced60bedd85214cf9921a4 (patch) | |
tree | 19cd4059c98338749a918392a91ca42533658577 /arch/mips | |
parent | 17099b1142f6c0359fca60a3464dea8fb30badea (diff) | |
download | linux-5a81299928f3d9abfaced60bedd85214cf9921a4.tar.gz linux-5a81299928f3d9abfaced60bedd85214cf9921a4.tar.bz2 linux-5a81299928f3d9abfaced60bedd85214cf9921a4.zip |
[MIPS] Workaround for RM7000 WAIT instruction aka erratum 38
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/kernel/cpu-probe.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c6b8b074a81a..06448a9656dc 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -75,6 +75,27 @@ static void r4k_wait_irqoff(void) local_irq_enable(); } +/* + * The RM7000 variant has to handle erratum 38. The workaround is to not + * have any pending stores when the WAIT instruction is executed. + */ +static void rm7k_wait_irqoff(void) +{ + local_irq_disable(); + if (!need_resched()) + __asm__( + " .set push \n" + " .set mips3 \n" + " .set noat \n" + " mfc0 $1, $12 \n" + " sync \n" + " mtc0 $1, $12 # stalls until W stage \n" + " wait \n" + " mtc0 $1, $12 # stalls until W stage \n" + " .set pop \n"); + local_irq_enable(); +} + /* The Au1xxx wait is available only if using 32khz counter or * external timer source, but specifically not CP0 Counter. */ int allow_au1k_wait; @@ -132,7 +153,6 @@ static inline void check_wait(void) case CPU_R4700: case CPU_R5000: case CPU_NEVADA: - case CPU_RM7000: case CPU_4KC: case CPU_4KEC: case CPU_4KSC: @@ -142,6 +162,10 @@ static inline void check_wait(void) cpu_wait = r4k_wait; break; + case CPU_RM7000: + cpu_wait = rm7k_wait_irqoff; + break; + case CPU_24K: case CPU_34K: cpu_wait = r4k_wait; |