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| author | David Daney <ddaney@caviumnetworks.com> | 2008-12-11 15:33:22 -0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-01-11 09:57:21 +0000 |
| commit | bd6d85c21a5adf24567fdb235aa8e7c8c95d5847 (patch) | |
| tree | 873767fba58ccbc1b4ae55aa8f16ef4b8ec5c246 /arch/mips | |
| parent | 5b3b16880f404ca54126210ca86141cceeafc0cf (diff) | |
| download | linux-bd6d85c21a5adf24567fdb235aa8e7c8c95d5847.tar.gz linux-bd6d85c21a5adf24567fdb235aa8e7c8c95d5847.tar.bz2 linux-bd6d85c21a5adf24567fdb235aa8e7c8c95d5847.zip | |
MIPS: For Cavium OCTEON handle hazards as per the R10000 handling.
For Cavium CPU, we treat the same as R10000, in that all hazards
are dealt with in hardware.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/hazards.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 2de638f84c86..43baed16a109 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -42,7 +42,7 @@ ASMMACRO(_ehb, /* * TLB hazards */ -#if defined(CONFIG_CPU_MIPSR2) +#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON) /* * MIPSR2 defines ehb for hazard avoidance @@ -138,7 +138,7 @@ do { \ __instruction_hazard(); \ } while (0) -#elif defined(CONFIG_CPU_R10000) +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |