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authorMaciej W. Rozycki <macro@imgtec.com>2016-10-31 16:26:24 +0000
committerRalf Baechle <ralf@linux-mips.org>2016-11-04 01:38:50 +0100
commit6daaa3266db9cc488612690e42c23b0763e2b49a (patch)
tree125b090f45799901b3f64166c1070e231580f10b /arch/mips
parent35938a00ba86ae7a7404b66b526968ca2b8d3127 (diff)
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MIPS: Remove FIR from ISA I FP signal context
Complement commit e50c0a8fa60d ("Support the MIPS32 / MIPS64 DSP ASE.") and remove the Floating Point Implementation Register (FIR) from the FP register set recorded in a signal context with MIPS I processors too, in line with the change applied to r4k_fpu.S. The `sc_fpc_eir' slot is unused according to our current ABI and the FIR register is read-only and always directly accessible from user software. [ralf@linux-mips.org: This is also required because the next commit depends on it.] Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14475/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/kernel/r2300_fpu.S6
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index c4c8c1b65be9..ce249eae91ce 100644
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -64,13 +64,9 @@ LEAF(_save_fp_context)
EX(swc1 $f29,(SC_FPREGS+232)(a0))
EX(swc1 $f30,(SC_FPREGS+240)(a0))
EX(swc1 $f31,(SC_FPREGS+248)(a0))
- EX(sw t1,(SC_FPC_CSR)(a0))
- cfc1 t0,$0 # implementation/version
jr ra
+ EX(sw t1,(SC_FPC_CSR)(a0))
.set pop
- .set nomacro
- EX(sw t0,(SC_FPC_EIR)(a0))
- .set macro
END(_save_fp_context)
/*