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authorÁlvaro Fernández Rojas <noltari@gmail.com>2020-06-17 12:50:38 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-11-17 21:52:46 +0100
commit226383600be58dcf2e070e4ac8a371640024fe54 (patch)
tree59a04cdc009a2985500fb9907dacc9375995a089 /arch/mips
parent8079cfba4c7b8cae900c27104b4512fa5ed1f021 (diff)
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mips: bmips: dts: add BCM6362 reset controller support
BCM6362 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/boot/dts/brcm/bcm6362.dtsi6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/brcm/bcm6362.dtsi b/arch/mips/boot/dts/brcm/bcm6362.dtsi
index c98f9111e3c8..eb10341b75ba 100644
--- a/arch/mips/boot/dts/brcm/bcm6362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm6362.dtsi
@@ -70,6 +70,12 @@
mask = <0x1>;
};
+ periph_rst: reset-controller@10000010 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x10000010 0x4>;
+ #reset-cells = <1>;
+ };
+
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>,