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authorPhil Sutter <n0-1@freewrt.org>2009-01-19 23:42:50 +0100
committerRalf Baechle <ralf@linux-mips.org>2009-01-30 21:33:00 +0000
commitdeb1003329b65456c4e6702cd3bcc698d565a11e (patch)
tree9cd346566d3f0881c8401c762704a31cdb0a8bc1 /arch/mips
parent94d2cc1b8b2bd2141e141a4f43bce9ab135bd9fd (diff)
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MIPS: RB532: Fix init of rb532_dev3_ctl_res
This register just contains the address of the actual resource, so initialisation has to be the same as cf_slot0_res and nand_slot0_res. Signed-off-by: Phil Sutter <n0-1@freewrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/rb532/gpio.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index b195f797c438..2f2cb8dc6531 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -55,8 +55,6 @@ static struct resource rb532_gpio_reg0_res[] = {
static struct resource rb532_dev3_ctl_res[] = {
{
.name = "dev3_ctl",
- .start = REGBASE + DEV3BASE,
- .end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
.flags = IORESOURCE_MEM,
}
};
@@ -251,6 +249,9 @@ int __init rb532_gpio_init(void)
/* Register our GPIO chip */
gpiochip_add(&rb532_gpio_chip->chip);
+ rb532_dev3_ctl_res[0].start = readl(IDT434_REG_BASE + DEV3BASE);
+ rb532_dev3_ctl_res[0].end = rb532_dev3_ctl_res[0].start + 0x1000;
+
r = rb532_dev3_ctl_res;
dev3.base = ioremap_nocache(r->start, r->end - r->start);