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authorThomas Gleixner <tglx@linutronix.de>2018-08-06 12:45:42 +0200
committerThomas Gleixner <tglx@linutronix.de>2018-08-06 12:45:42 +0200
commit9e90c7985229430428dc9ba0ec7fe422901b456d (patch)
treecae2072feba8cc433a32d96568bbcf36070bd6e5 /arch/openrisc/include
parent4f7799d96e6621ce584df60739e1480a6fd89f0a (diff)
parenta8db74564b0c634667e1722264bde303d296f566 (diff)
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Merge tag 'irqchip-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier: - GICv3 ITS LPI allocation revamp - GICv3 support for hypervisor-enforced LPI range - GICv3 ITS conversion to raw spinlock
Diffstat (limited to 'arch/openrisc/include')
-rw-r--r--arch/openrisc/include/asm/pgalloc.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/openrisc/include/asm/pgalloc.h b/arch/openrisc/include/asm/pgalloc.h
index 3e1a46615120..8999b9226512 100644
--- a/arch/openrisc/include/asm/pgalloc.h
+++ b/arch/openrisc/include/asm/pgalloc.h
@@ -98,8 +98,12 @@ static inline void pte_free(struct mm_struct *mm, struct page *pte)
__free_page(pte);
}
+#define __pte_free_tlb(tlb, pte, addr) \
+do { \
+ pgtable_page_dtor(pte); \
+ tlb_remove_page((tlb), (pte)); \
+} while (0)
-#define __pte_free_tlb(tlb, pte, addr) tlb_remove_page((tlb), (pte))
#define pmd_pgtable(pmd) pmd_page(pmd)
#define check_pgt_cache() do { } while (0)