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| author | Davidlohr Bueso <dave@stgolabs.net> | 2015-12-31 12:09:13 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2016-01-12 20:46:46 +0200 |
| commit | 5a1b26d7c629915446222ebe77d16567c98426ff (patch) | |
| tree | 7e10866d7e695a1c345d4b89935e7981f370d796 /arch/powerpc/include/asm/barrier.h | |
| parent | afd2ff9b7e1b367172f18ba7f693dfb62bdcb2dc (diff) | |
| download | linux-5a1b26d7c629915446222ebe77d16567c98426ff.tar.gz linux-5a1b26d7c629915446222ebe77d16567c98426ff.tar.bz2 linux-5a1b26d7c629915446222ebe77d16567c98426ff.zip | |
lcoking/barriers, arch: Use smp barriers in smp_store_release()
With commit b92b8b35a2e ("locking/arch: Rename set_mb() to smp_store_mb()")
it was made clear that the context of this call (and thus set_mb)
is strictly for CPU ordering, as opposed to IO. As such all archs
should use the smp variant of mb(), respecting the semantics and
saving a mandatory barrier on UP.
Signed-off-by: Davidlohr Bueso <dbueso@suse.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: <linux-arch@vger.kernel.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: dave@stgolabs.net
Link: http://lkml.kernel.org/r/1445975631-17047-3-git-send-email-dave@stgolabs.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/include/asm/barrier.h')
| -rw-r--r-- | arch/powerpc/include/asm/barrier.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h index 0eca6efc0631..a7af5fb7b914 100644 --- a/arch/powerpc/include/asm/barrier.h +++ b/arch/powerpc/include/asm/barrier.h @@ -34,7 +34,7 @@ #define rmb() __asm__ __volatile__ ("sync" : : : "memory") #define wmb() __asm__ __volatile__ ("sync" : : : "memory") -#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0) +#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0) #ifdef __SUBARCH_HAS_LWSYNC # define SMPWMB LWSYNC |